Datasheet > 27LV256-30I/VS

27LV256-30I/VS

更新时间： 2024-02-12 18:52:26

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美国微芯 - MICROCHIP		/
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12页	64K
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27LV256-30I/VS 数据手册

27LV256

FIGURE 1-2: PROGRAMMING WAVEFORMS

Program

Verify

VIH

Address

Data

Address Stable

VIL

VIH

VIL

tAS

tDS

tAH

High Z

Data Stable

Data Out Valid

tDF

(1)

tDH

13.0V(2)

5.0V

6.5V(2)

5.0V

VIH

VPP

VCC

tVPS

tVCS

VIL

tOES

tPW

tOE

(1)

VIH

tOPW

VIL

Notes:

(1) tDF and tOE are characteristics of the device but must be accommodated by the programmer

(2) VCC = 6.5V ±0.25V, VPP = VH = 13.0V ±0.25V for express algorithm

TABLE 1-6:

MODES

Operation Mode

VPP

O0 - O7

Read

VIL

VIH

VIL

VIH

VIL

VIH

VCC

DOUT

DIN

Program

Program Verify

Program Inhibit

Standby

DOUT

High Z

VCC

High Z

Output Disable

Identity

VIH

VIL

High Z

Identity Code

X = Don’t Care

1.2

Read Mode

For Read operations, if the addresses are stable, the

address access time (tACC) is equal to the delay from

CE to output (tCE). Data is transferred to the output

after a delay from the falling edge of OE (tOE).

(See Timing Diagrams and AC Characteristics)

Read Mode is accessed when:

a) the CE pin is low to power up (enable) the chip

b) the OE pin is low to gate the data to the output

pins

1996 Microchip Technology Inc.

DS11020F-page 5

1 2 3 456 7 8...12

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