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27C256-10 PDF预览

27C256-10

更新时间： 2024-02-24 02:39:11
品牌 Logo 应用领域
旺宏电子 - Macronix 可编程只读存储器电动程控只读存储器
页数 文件大小 规格书
15页 765K
描述
256K-BIT [32K x 8] CMOS EPROM

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中文翻译

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27C256-10 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：8 X 13.40 MM, VSOP-28针数：28
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.32.00.71风险等级：5.62
Is Samacsys：N最长访问时间：100 ns
I/O 类型：COMMONJESD-30 代码：R-PDSO-G28
JESD-609代码：e0长度：11.8 mm
内存密度：262144 bit内存集成电路类型：OTP ROM
内存宽度：8功能数量：1
端子数量：28字数：32768 words
字数代码：32000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：32KX8输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TSOP1
封装等效代码：TSSOP28,.53,22封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
编程电压：13 V认证状态：Not Qualified
座面最大高度：1.2 mm最大待机电流：0.0001 A
子类别：OTP ROMs最大压摆率：0.025 mA
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.55 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：8 mm
Base Number Matches：1

27C256-10 数据手册

 浏览型号27C256-10的Datasheet PDF文件第1页浏览型号27C256-10的Datasheet PDF文件第3页浏览型号27C256-10的Datasheet PDF文件第4页浏览型号27C256-10的Datasheet PDF文件第5页浏览型号27C256-10的Datasheet PDF文件第6页浏览型号27C256-10的Datasheet PDF文件第7页 
MX27C256  
FUNCTIONAL DESCRIPTION  
AUTO IDENTIFY MODE  
THE PROGRAMMING OF THE MX27C256  
Theautoidentifymodeallowsthereadingoutofabinary  
code from an EPROM that will identify its manufacturer  
and device type. This mode is intended for use by  
programming equipment for the purpose of  
automatically matching the device to be programmed  
with its corresponding programming algorithm. This  
mode is functional in the 25°C ± 5°C ambient  
temperature range that is required when programming  
the MX27C256.  
When the MX27C256 is delivered, or it is erased, the  
chip has all 256K bits in the "ONE" or HIGH state.  
"ZEROs" are loaded into the MX27C256 through the  
procedure of programming.  
Forprogramming, thedatatobeprogrammedisapplied  
with 8 bits in parallel to the data pins.  
VCCmustbeappliedsimultaneouslyorbeforeVPP,and  
removed simultaneously or after VPP. When  
programming an MXIC EPROM, a 0.1uF capacitor is  
required across VPP and ground to suppress spurious  
voltage transients which may damage the device.  
To activate this mode, the programming equipment  
must force 12.0 ±0.5 (VH) on address line A9 of the  
device. Two identifier bytes may then be sequenced  
fromthedeviceoutputsbytogglingaddresslineA0from  
VIL to VIH. All other address lines must be held at VIL  
during auto identify mode.  
FAST PROGRAMMING  
Byte 0 ( A0 = VIL) represents the manufacturer code,  
andbyte1(A0=VIH),thedeviceidentifiercode. Forthe  
MX27C256, these two identifier bytes are given in the  
Mode Select Table. All identifiers for manufacturer and  
devicecodeswillpossessoddparity,withtheMSB(Q7)  
defined as the parity bit.  
Thedeviceissetupinthefastprogrammingmodewhen  
the programming voltage VPP = 12.75V is applied, with  
VCC = 6.25 V and OE = VIH (Algorithm is shown in  
Figure 1). The programming is achieved by applying a  
single TTL low level 100us pulse to the CE input after  
addresses and data line are stable. If the data is not  
verified, an additional pulse is applied for a maximum of  
25 pulses. This process is repeated while sequencing  
through each address of the device. When the  
programmingmodeiscompleted,thedatainalladdress  
is verified at VCC = VPP = 5V ±10%.  
READ MODE  
TheMX27C256hastwocontrolfunctions,bothofwhich  
must be logically satisfied in order to obtain data at the  
outputs. Chip Enable (CE) is the power control and  
should be used for device selection. Output Enable  
(OE) is the output control and should be used to gate  
datatotheoutputpins,independentofdeviceselection.  
Assuming that addresses are stable, address access  
time(tACC)isequaltothedelayfromCEtooutput(tCE).  
DataisavailableattheoutputstOEafterthefallingedge  
ofOE,assumingthatCEhasbeenLOWandaddresses  
have been stable for at least tACC - tOE.  
PROGRAM INHIBIT MODE  
Programming of multiple MX27C256s in parallel with  
different data is also easily accomplished by using the  
Program Inhibit Mode. Except for CE and OE, all like  
inputs of the parallel MX27C256 may be common. A  
TTL low-level program pulse applied to an MX27C256  
CE input with VPP = 12.5 ±0.5 V and OE HIGH will  
program that MX27C256. A high-level CE input inhibits  
the other MX27C256s from being programmed.  
STANDBY MODE  
The MX27C256 has a CMOS standby mode which  
reduces the maximum Vcc current to 100 uA. It is  
placed in CMOS standby when CE is at VCC ±0.3 V.  
The MX27C256 also has a TTL-standby mode which  
reduces the maximum VCC current to 1.5 mA. It is  
placed in TTL-standby when CE is at VIH. When in  
standby mode, the outputs are in a high-impedance  
state, independent of the OE input.  
PROGRAM VERIFY MODE  
Verification should be performed on the programmed  
bits to determine that they were correctly programmed.  
The verification should be performed with CE and OE  
at VIL, and VPP at its programming voltage.  
REV.5.6, AUG. 26, 2003  
P/N:PM0203  
2
1234567...15

中文翻译

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