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25LC040X-ST PDF预览

25LC040X-ST

更新时间： 2024-11-28 23:19:23
品牌 Logo 应用领域
其他 - ETC 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
12页 157K
描述
SPI Serial EEPROM

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中文翻译

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25LC040X-ST 数据手册

 浏览型号25LC040X-ST的Datasheet PDF文件第2页浏览型号25LC040X-ST的Datasheet PDF文件第3页浏览型号25LC040X-ST的Datasheet PDF文件第4页浏览型号25LC040X-ST的Datasheet PDF文件第5页浏览型号25LC040X-ST的Datasheet PDF文件第6页浏览型号25LC040X-ST的Datasheet PDF文件第7页 
25AA040/25LC040/25C040  
4K SPI Bus Serial EEPROM  
M
™
PACKAGE TYPES  
DEVICE SELECTION TABLE  
Part  
Number  
VCC  
Range  
Max Clock  
Frequency  
Temp  
Ranges  
PDIP/SOIC  
1
2
3
4
8
7
6
5
VCC  
HOLD  
SCK  
SI  
CS  
SO  
25AA040  
25LC040  
25C040  
1.8-5.5V  
2.5-5.5V  
4.5-5.5V  
1 MHz  
2 MHz  
3 MHz  
C,I  
C,I  
C,I,E  
WP  
VSS  
FEATURES  
• Low power CMOS technology  
- Write current: 3 mA typical  
- Read current: 500 µA typical  
- Standby current: 500 nA typical  
• 512 x 8 bit organization  
TSSOP  
1
2
3
4
8
7
6
5
SCK  
SI  
VSS  
WP  
HOLD  
VCC  
CS  
• 16 byte page  
• Write cycle time: 5ms max.  
• Self-timed ERASE and WRITE cycles  
• Block write protection  
SO  
- Protect none, 1/4, 1/2, or all of array  
• Built-in write protection  
- Power on/off data protection circuitry  
- Write enable latch  
BLOCK DIAGRAM  
Status  
Register  
- Write protect pin  
• Sequential read  
HV Generator  
• High reliability  
- Endurance: 1M cycles (guaranteed)  
- Data retention: > 200 years  
- ESD protection: > 4000 V  
• 8-pin PDIP, SOIC, and TSSOP packages  
• Temperature ranges supported:  
EEPROM  
Array  
Memory  
Control  
Logic  
X
I/O Control  
Logic  
- Commercial (C):  
- Industrial (I):  
0°C to +70°C  
-40°C to +85°C  
-40°C to +125°C  
Dec  
- Automotive (E) (25C040):  
Page Latches  
DESCRIPTION  
SI  
The Microchip Technology Inc. 25AA040/25LC040/  
25C040 (25xx040 ) is a 4K bit serial Electrically Eras-  
*
Y Decoder  
SO  
able PROM. The memory is accessed via a simple  
Serial Peripheral Interface (SPI) compatible serial bus.  
The bus signals required are a clock input (SCK) plus  
separate data in (SI) and data out (SO) lines. Access to  
the device is controlled through a chip select (CS)  
input.  
CS  
SCK  
Sense Amp.  
R/W Control  
HOLD  
WP  
VCC  
VSS  
Communication to the device can be paused via the  
hold pin (HOLD). While the device is paused, transi-  
tions on its inputs will be ignored, with the exception of  
chip select, allowing the host to service higher priority  
interrupts. Also, write operations to the device can be  
disabled via the write protect pin (WP).  
*25xx040 is used in this document as a generic part number for the 25AA040/25LC040/25C040 devices.  
SPI is a trademark of Motorola.  
1998 Microchip Technology Inc.  
DS21204B-page 1  
Powered by ICminer.com Electronic-Library Service CopyRight 2003  
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