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24LCS52/ST PDF预览

24LCS52/ST

更新时间: 2024-11-20 23:19:15
品牌 Logo 应用领域
其他 - ETC 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
13页 196K
描述
SERIAL EEPROM|256X8|CMOS|TSSOP|8PIN|PLASTIC

24LCS52/ST 数据手册

 浏览型号24LCS52/ST的Datasheet PDF文件第2页浏览型号24LCS52/ST的Datasheet PDF文件第3页浏览型号24LCS52/ST的Datasheet PDF文件第4页浏览型号24LCS52/ST的Datasheet PDF文件第5页浏览型号24LCS52/ST的Datasheet PDF文件第6页浏览型号24LCS52/ST的Datasheet PDF文件第7页 
24LCS52  
2K 2.2V I2CSerial EEPROM with Software Write Protect  
FEATURES  
PACKAGE TYPES  
PDIP/SOIC  
• Single supply with operation down to 2.2V  
• Low power CMOS technology  
- 1 mA active current typical  
A0  
1
8
Vcc  
- 10 µA standby current typical at 5.5V  
- 5 µA standby current typical at 3.0V  
• Organized as a single block of 256 bytes (256 x 8)  
• Software write protection for lower 128 bytes  
• Hardware write protection for entire array  
• 2-wire serial interface bus, I2C™ compatible  
• 100kHz (2.2V) and 400kHz (5V) compatibility  
• Self-timed write cycle (including auto-erase)  
• Page-write buffer for up to 16 bytes  
• 3.5 ms typical write cycle time for page-write  
• 1,000,000 erase/write cycles guaranteed  
• ESD protection >4,000V  
A1  
A2  
2
3
7
6
WP  
SCL  
Vss  
4
5
SDA  
TSSOP  
• Data retention > 200 years  
• 8-pin DIP, SOIC or TSSOP packages  
• Available for extended temperature ranges  
1
2
3
4
8
7
6
5
Vcc  
WP  
SCL  
SDA  
A0  
A1  
A2  
- Commercial (C):  
- Industrial (I):  
0°C to +70°C  
-40°C to +85°C  
Vss  
DESCRIPTION  
The Microchip Technology Inc. 24LCS52 is a 2K bit  
Electrically Erasable PROM capable of operation  
across a broad voltage range (2.2V to 5.5V). This  
device has a software write protect feature for the lower  
half of the array, as well as an external pin that can be  
used to write protect the entire array. The software write  
protect feature is enabled by sending the device a spe-  
cial command, and once this feature has been enabled,  
it cannot be reversed. In addition to the software pro-  
tect feature, there is a WP pin that can be used to write  
protect the entire array, regardless of whether the soft-  
ware write protect register has been written or not. This  
allows the system designer to protect none, half or all  
of the array, depending on the application. The device  
is organized as a single block of 256 x 8-bit memory  
with a 2-wire serial interface. Low voltage design per-  
mits operation down to 2.2 volts with typical standby  
and active currents of only 5 µA and 1 mA respectively.  
The device has a page-write capability for up to 16  
bytes of data. The device is available in the standard 8-  
pin DIP, 8-pin SOIC and TSSOP packages.  
BLOCK DIAGRAM  
WP  
A0 A1 A2  
HV Generator  
Software write  
protected area  
(00h-7Fh)  
I/O  
Control  
Logic  
Memory  
Control  
Logic  
XDEC  
Standard  
Array  
SDA  
SCL  
Vcc  
Vss  
Write Protect  
Circuitry  
YDEC  
SENSE AMP  
R/W CONTROL  
I2C is a trademark of Philips Corporation.  
1999 Microchip Technology Inc.  
DS21166E-page 1  

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