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24LC64T-I/SM

更新时间： 2024-02-10 01:26:21

品牌	Logo	应用领域
美国微芯 - MICROCHIP		存储内存集成电路光电二极管双倍数据速率可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
页数	文件大小	规格书
28页	418K
描述
64K I2C⑩ Serial EEPROM

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数据手册

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24LC64T-I/SM 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SOIC
包装说明：	4.40 MM, ROHS COMPLIANT, PLASTIC, TSSOP-8	针数：	8
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.51	Factory Lead Time：	6 weeks
风险等级：	1.02	Is Samacsys：	N
其他特性：	DATA RETENTION > 200 YEARS; 1000000 ERASE/WRITE CYCLES GUARANTEED	最大时钟频率 (fCLK)：	0.4 MHz
数据保留时间-最小值：	200	耐久性：	1000000 Write/Erase Cycles
I2C控制字节：	1010DDDR	JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e3	长度：	4.4 mm
内存密度：	65536 bit	内存集成电路类型：	EEPROM
内存宽度：	8	湿度敏感等级：	1
功能数量：	1	端子数量：	8
字数：	8192 words	字数代码：	8000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	8KX8
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装等效代码：	TSSOP8,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	并行/串行：	SERIAL
峰值回流温度（摄氏度）：	260	电源：	2/5 V
认证状态：	Not Qualified	座面最大高度：	1.1 mm
串行总线类型：	I2C	最大待机电流：	0.000001 A
子类别：	EEPROMs	最大压摆率：	0.003 mA
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	2.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	40	宽度：	3 mm
最长写入周期时间 (tWC)：	5 ms	写保护：	HARDWARE
Base Number Matches：	1

24LC64T-I/SM 数据手册

24AA64/24LC64/24FC64

3.4

Data Valid (D)

2.0

FUNCTIONAL DESCRIPTION

The state of the data line represents valid data when,

after a Start condition, the data line is stable for the

duration of the high period of the clock signal.

The 24XX64 supports a bidirectional, 2-wire bus and

data transmission protocol. A device that sends data

onto the bus is defined as transmitter, while a device

receiving data is defined as a receiver. The bus has to

be controlled by a master device which generates the

Serial Clock (SCL), controls the bus access and

generates the Start and Stop conditions, while the

24XX64 works as slave. Both master and slave can

operate as transmitter or receiver, but the master

device determines which mode is activated.

The data on the line must be changed during the low

period of the clock signal. There is one clock pulse per

bit of data.

Each data transfer is initiated with a Start condition and

terminated with a Stop condition. The number of data

bytes transferred between Start and Stop conditions is

determined by the master device and is, theoretically,

unlimited (although only the last thirty two will be stored

when doing a write operation). When an overwrite does

occur, it will replace data in a first-in first-out (FIFO)

fashion.

3.0

BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy

3.5

Acknowledge

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes in

the data line while the clock line is high will be

interpreted as a Start or Stop condition

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The master device must generate an extra clock

pulse which is associated with this Acknowledge bit.

Accordingly, the following bus conditions have been

defined (Figure 3-1).

Note:

The 24XX64 does not generate any

Acknowledge bits if an internal

programming cycle is in progress.

3.1

Bus Not Busy (A)

The device that acknowledges has to pull down the

SDA line during the Acknowledge clock pulse in such a

way that the SDA line is stable low during the high

period of the acknowledge related clock pulse. Of

course, setup and hold times must be taken into

account. During reads, a master must signal an end of

data to the slave by not generating an Acknowledge bit

on the last byte that has been clocked out of the slave.

In this case, the slave (24XX64) will leave the data line

high to enable the master to generate the Stop

condition.

Both data and clock lines remain high.

3.2

Start Data Transfer (B)

A high-to-low transition of the SDA line while the clock

(SCL) is high determines a Start condition. All

commands must be preceded by a Start condition.

3.3

Stop Data Transfer (C)

A low-to-high transition of the SDA line while the clock

(SCL) is high determines a Stop condition. All

operations must be ended with a Stop condition.

FIGURE 3-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A)

(B)

(D)

SCL

SDA

Start

Condition

Stop

Condition

Address or

Acknowledge

Valid

Data

Allowed

to Change

DS21189L-page 5

1 2 3 456 7 8...28

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与24LC64T-I/SM相关器件

型号	品牌	描述	获取价格	数据表
24LC64TI-/SM	MICROCHIP	8K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 5.28 MM, ROHS COMPLIANT, PLASTIC, SOIJ-8	获取价格
24LC64T-I/SMG	MICROCHIP	8K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 5.28 MM, ROHS COMPLIANT, PLASTIC, SOIJ-8	获取价格
24LC64T-I/SMRVA	MICROCHIP	8K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 5.28 MM, ROHS COMPLIANT, PLASTIC, SOIJ-8	获取价格
24LC64TI/SN	MICROCHIP	暂无描述	获取价格
24LC64T-I/SN	MICROCHIP	64K I2C⑩ Serial EEPROM	获取价格
24LC64TI-/SN	MICROCHIP	8K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 3.90 MM, ROHS COMPLIANT, PLASTIC, SOIC-8	获取价格

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