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24LC1026T-I/ST PDF预览

24LC1026T-I/ST

更新时间: 2023-01-03 06:18:08
品牌 Logo 应用领域
美国微芯 - MICROCHIP 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
32页 685K
描述
I2C/2-WIRE SERIAL EEPROM

24LC1026T-I/ST 数据手册

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24AA1026/24LC1026/24FC1026  
2.0  
PIN DESCRIPTIONS  
The descriptions of the pins are listed in Table 2-1.  
TABLE 2-1:  
Name  
PIN FUNCTION TABLE  
PDIP  
SOIJ  
SOIC  
TSSOP  
Function  
NC  
A1  
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
Not Connected  
User Configurable Chip Select  
User Configurable Chip Select  
Ground  
A2  
VSS  
SDA  
SCL  
WP  
VCC  
Serial Data  
Serial Clock  
Write-Protect Input  
+1.7 to 5.5V (24AA1026)  
+2.5 to 5.5V (24LC1026)  
+1.8 to 5.5V (24FC1026)  
2.1  
A1, A2 Chip Address Inputs  
The A1 and A2 inputs are used by the 24XX1026 for  
multiple device operations. The levels on these inputs  
are compared with the corresponding bits in the slave  
address. The chip is selected if the comparison is true.  
Up to four devices may be connected to the same bus  
by using different Chip Select bit combinations. In most  
applications, the chip address inputs A1 and A2 are  
hard-wired to logic ‘0’ or logic ‘1’. For applications in  
which these pins are controlled by a microcontroller or  
other programmable device, the chip address pins  
must be driven to logic ‘0’ or logic ‘1’ before normal  
device operation can proceed.  
2.2  
Serial Data (SDA)  
This is a bidirectional pin used to transfer addresses  
and data into and data out of the device. It is an open-  
drain terminal, therefore, the SDA bus requires a pull-  
up resistor to VCC (typical 10 kfor 100 kHz, 2 kfor  
400 kHz and 1 MHz).  
For normal data transfer SDA is allowed to change only  
during SCL low. Changes during SCL high are  
reserved for indicating the Start and Stop conditions.  
2.3  
Serial Clock (SCL)  
This input is used to synchronize the data transfer from  
and to the device.  
2.4  
Write-Protect (WP)  
This pin must be connected to either VSS or VCC. If tied  
to VSS, write operations are enabled. If tied to VCC,  
write operations are inhibited, but read operations are  
not affected.  
2011-2013 Microchip Technology Inc.  
DS20002270D-page 5  

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