Datasheet > 24LC1026T-I/ST

24LC1026T-I/ST

更新时间： 2023-01-03 06:18:08

品牌	Logo	应用领域
美国微芯 - MICROCHIP		可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
32页	685K
描述
I2C/2-WIRE SERIAL EEPROM

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中文翻译

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数据手册
替代型号

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24LC1026T-I/ST 数据手册

24AA1026/24LC1026/24FC1026

The data on the line must be changed during the low

period of the clock signal. There is one bit of data per

clock pulse.

4.0

BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

Each data transfer is initiated with a Start condition and

terminated with a Stop condition. The number of the

data bytes transferred between the Start and Stop

conditions is determined by the master device.

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes in

the data line while the clock line is high will be

interpreted as a Start or Stop condition.

4.5

Acknowledge

Accordingly, the following bus conditions have been

defined (Figure 4-1).

Each receiving device, when addressed, is obliged to

generate an Acknowledge signal after the reception of

each byte. The master device must generate an extra

clock pulse which is associated with this Acknowledge

bit.

4.1

Bus Not Busy (A)

Both data and clock lines remain high.

Note:

The 24XX1026 does not generate any

Acknowledge bits if an internal program-

ming cycle is in progress, however, the

control byte that is being polled must

match the control byte used to initiate the

write cycle.

4.2

Start Data Transfer (B)

A high-to-low transition of the SDA line while the clock

(SCL) is high determines a Start condition. All

commands must be preceded by a Start condition.

A device that acknowledges must pull-down the SDA

line during the Acknowledge clock pulse in such a way

that the SDA line is stable low during the high period of

the acknowledge related clock pulse. Of course, setup

and hold times must be taken into account. During

reads, a master must signal an end of data to the slave

by NOT generating an Acknowledge bit on the last byte

that has been clocked out of the slave. In this case, the

slave (24XX1026) will leave the data line high to enable

the master to generate the Stop condition.

4.3

Stop Data Transfer (C)

A low-to-high transition of the SDA line while the clock

(SCL) is high determines a Stop condition. All

operations must end with a Stop condition.

4.4

Data Valid (D)

The state of the data line represents valid data when,

after a Start condition, the data line is stable for the

duration of the high period of the clock signal.

FIGURE 4-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A)

(B)

(D)

SCL

SDA

Start

Condition

Address or

Acknowledge

Valid

Data

Allowed

To Change

Stop

Condition

FIGURE 4-2:

ACKNOWLEDGE TIMING

Acknowledge

Bit

SCL

SDA

Data from transmitter

The transmitter must release the SDA line at this

point allowing the receiver to pull the SDA line low

to acknowledge the previous eight bits of data.

The receiver must release the SDA line at this

point so the transmitter can continue sending

data.

 2011-2013 Microchip Technology Inc.

DS20002270D-page 7

1...4 5 678 9 10...32

中文翻译

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24LC1026T-I/ST 替代型号

型号	品牌	替代类型	描述	数据表
24LC1026T-E/ST	MICROCHIP	完全替代	I2C/2-WIRE SERIAL EEPROM

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