Datasheet > 24C65TI/SMG

24C65TI/SMG

更新时间： 2024-02-08 20:20:46

品牌	Logo	应用领域
美国微芯 - MICROCHIP		可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
页数	文件大小	规格书
24页	296K
描述
8K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 0.207 INCH, EIAJ, PLASTIC, SOIC-8

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24C65TI/SMG 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SOIC
包装说明：	0.207 INCH, EIAJ, PLASTIC, SOIC-8	针数：	8
Reach Compliance Code：	compliant	风险等级：	5.19
最大时钟频率 (fCLK)：	0.4 MHz	JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e3	长度：	5.28 mm
内存密度：	65536 bit	内存集成电路类型：	EEPROM
内存宽度：	8	功能数量：	1
端子数量：	8	字数：	8192 words
字数代码：	8000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	8KX8	输出特性：	OPEN-DRAIN
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
并行/串行：	SERIAL	峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified	座面最大高度：	2.03 mm
串行总线类型：	I2C	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	MATTE TIN
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	40
宽度：	5.2 mm	最长写入周期时间 (tWC)：	5 ms
Base Number Matches：	1

24C65TI/SMG 数据手册

24AA65/24LC65/24C65

3.3

Stop Data Transfer (C)

2.0

FUNCTIONAL DESCRIPTION

A low-to-high transition of the SDA line while the clock

(SCL) is high determines a Stop condition. All

operations must be ended with a Stop condition.

The 24XX65 supports a bidirectional two-wire bus and

data transmission protocol. A device that sends data

onto the bus is defined as transmitter, and a device

receiving data as receiver. The bus must be controlled

by a master device which generates the serial clock

(SCL), controls the bus access and generates the Start

and Stop conditions, while the 24XX65 works as slave.

Both master and slave can operate as transmitter or

receiver, but the master device determines which mode

is activated.

3.4

Data Valid (D)

The state of the data line represents valid data when,

after a Start condition, the data line is stable for the

duration of the high period of the clock signal.

The data on the line must be changed during the low

period of the clock signal. There is one clock pulse per

bit of data.

3.0

BUS CHARACTERISTICS

Each data transfer is initiated with a Start condition and

terminated with a Stop condition. The number of the

data bytes transferred between the Start and Stop

conditions is determined by the master device.

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes in

the data line while the clock line is high will be

interpreted as a Start or Stop condition.

3.5

Acknowledge

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The master device must generate an extra clock

pulse which is associated with this Acknowledge bit.

Accordingly, the following bus conditions have been

defined (Figure 3-1).

Note:

The 24XX65 does not generate any

Acknowledge bits if an internal program-

ming cycle is in progress.

3.1

Bus not Busy (A)

Both data and clock lines remain high.

A device that acknowledges must pull down the SDA

line during the Acknowledge clock pulse in such a way

that the SDA line is stable low during the high period of

the acknowledge related clock pulse. Of course, setup

and hold times must be taken into account. During

reads, a master must signal an end of data to the slave

by NOT generating an Acknowledge bit on the last byte

that has been clocked out of the slave. In this case, the

slave (24XX65) must leave the data line high to enable

the master to generate the Stop condition.

3.2

Start Data Transfer (B)

A high-to-low transition of the SDA line while the clock

(SCL) is high determines a Start condition. All

commands must be preceded by a Start condition.

FIGURE 3-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A)

(B)

(D)

(C)

(A)

SCL

SDA

Start

Condition

Stop

Condition

Address or

Acknowledge

Valid

Data

Allowed

To Change

 2003 Microchip Technology Inc.

DS21073J-page 5

1 2 3 456 7 8...24

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与24C65TI/SMG相关器件

型号	品牌	描述	获取价格	数据表
24C65T-I/SMG	MICROCHIP	8K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 5.28 MM, ROHS COMPLIANT, PLASTIC, SOIJ-8	获取价格
24-CBSA-0.5X0.75X0.2	ETC	24 SERIES CBS SHIELD ASSEMBLY -	获取价格
24-CBSA-0.5X1.0X0.2	ETC	24 SERIES CBS SHIELD ASSEMBLY -	获取价格
24-CBSA-0.5X1.25X0.2	ETC	24 SERIES CBS SHIELD ASSEMBLY -	获取价格
24-CBSA-0.5X1.75X0.2	ETC	24 SERIES CBS SHIELD ASSEMBLY -	获取价格
24-CBSA-0.5X2.0X0.25	ETC	24-CBSA-0.5X2.0X0.25--24S320--CI	获取价格

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