Datasheet > 23S09E-1HDCG8

23S09E-1HDCG8

更新时间： 2022-09-15 17:49:16

品牌	Logo	应用领域
艾迪悌 - IDT		时钟
页数	文件大小	规格书
8页	69K
描述
3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE

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23S09E-1HDCG8 数据手册

IDT23S09E

3.3VZERODELAYCLOCKBUFFER

COMMERCIALANDINDUSTRIALTEMPERATURERANGES

PINCONFIGURATION

ABSOLUTEMAXIMUMRATINGS⁽¹⁾

Symbol

Rating

Max.

–0.5to+4.6

–0.5to+5.5

–0.5to

VDD+0.5

–50

Unit

VDD

SupplyVoltageRange

InputVoltageRange(REF)

InputVoltageRange

(except REF)

REF

CLKA1

CLKA2

VDD

CLKOUT

CLKA4

CLKA3

VDD

(2)

IIK (VI < 0)

IO (VO = 0 to VDD)

VDD or GND

TA = 55°C

(instillair)⁽³⁾

TSTG

InputClampCurrent

ContinuousOutputCurrent

ContinuousCurrent

±50

GND

±100

MaximumPowerDissipation

0.7

CLKB1

CLKB2

CLKB4

CLKB3

StorageTemperatureRange

CommercialTemperature

Range

–65to+150

0 to +70

°C

Operating

Temperature

Operating

IndustrialTemperature

Range

-40to+85

°C

SOIC/ TSSOP

TOP VIEW

Temperature

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

2. The input and output negative-voltage ratings may be exceeded if the input and output

clamp-current ratings are observed.

3. The maximum package power dissipation is calculated using a junction temperature

of 150°C and a board trace length of 750 mils.

APPLICATIONS:

•

SDRAM

Telecom

Datacom

PC Motherboards/Workstations

Critical Path Delay Designs

PINDESCRIPTION

Pin Name

REF⁽¹⁾

Pin Number

Type

FunctionalDescription

Inputreferenceclock, 5Volttolerantinput

Output clock for bank A

3.3V Supply

CLKA1⁽²⁾

CLKA2⁽²⁾

VDD

Out

PWR

GND

Out

4, 13

5, 12

GND

Ground

CLKB1⁽²⁾

CLKB2⁽²⁾

S2⁽³⁾

Output clock for bank B

Select input Bit 2

S1⁽³⁾

Select input Bit 1

CLKB3⁽²⁾

CLKB4⁽²⁾

CLKA3⁽²⁾

CLKA4⁽²⁾

CLKOUT⁽²⁾

Out

Output clock for bank B

Output clock for bank A

Outputclock, internalfeedbackonthispin

NOTES:

1. Weak pull down.

2. Weak pull down on all outputs.

3. Weak pull ups on these inputs.

123 4 5 6 7 8

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