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2305-1PGGI PDF预览

2305-1PGGI

更新时间: 2024-11-07 12:28:15
品牌 Logo 应用领域
艾迪悌 - IDT RC网络时钟
页数 文件大小 规格书
12页 186K
描述
3.3V ZERO DELAY CLOCK BUFFER No external RC network required

2305-1PGGI 数据手册

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IDT2305  
3.3V ZERO DELAY  
CLOCK BUFFER  
FEATURES:  
DESCRIPTION:  
• Phase-Lock Loop Clock Distribution  
• 10MHz to 133MHz operating frequency  
• Distributes one clock input to one bank of five outputs  
• Zero Input-Output Delay  
The IDT2305 is a high-speed phase-lock loop (PLL) clock buffer,  
designed to address high-speed clock distribution applications. The zero  
delay is achieved by aligning the phase between the incoming clock and  
the output clock, operable within the range of 10 to 133MHz.  
• Output Skew < 250ps  
The IDT2305 is an 8-pin version of the IDT2309. IDT2305 accepts one  
referenceinput,anddrivesoutfivelowskewclocks.The-1Hversionofthis  
device operates, up to 133MHz frequency and has a higher drive than the  
-1 device. All parts have on-chip PLLs which lock to an input clock on the  
REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT  
pad. In the absence of an input clock, the IDT2305 enters power down. In  
• Low jitter <200 ps cycle-to-cycle  
• IDT2305-1 for Standard Drive  
• IDT2305-1H for High Drive  
• No external RC network required  
• Operates at 3.3V VDD  
• Power down mode  
• Available in SOIC/TSSOP packages  
this mode, the device will draw less than 25µA, the outputs are tri-stated,  
and the PLL is not running, resulting in a significant reduction of power.  
The IDT2305 is characterized for both Industrial and Commercial  
NOTE: EOL for non-green parts to occur on  
5/13/10 per PDN U-09-01  
operation.  
FUNCTIONALBLOCKDIAGRAM  
8
CLKOUT  
3
CLK1  
PLL  
1
Control  
Logic  
REF  
2
CLK2  
CLK3  
CLK4  
5
7
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
AUGUST 2009  
1
c
2009 Integrated Device Technology, Inc.  
DSC 5174/8  

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