Datasheet > 14174B

14174B

更新时间： 2024-11-21 02:53:31

品牌	Logo	应用领域
安森美 - ONSEMI		触发器
页数	文件大小	规格书
8页	96K
描述
Hex Type D Flip-Flop

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14174B 数据手册

MC14174B

Hex Type D Flip-Flop

The MC14174B hex type D flip–flop is constructed with MOS

P–channel and N–channel enhancement mode devices in a single

monolithic structure. Data on the D inputs which meets the setup time

requirements is transferred to the Q outputs on the positive edge of the

clock pulse. All six flip–flops share common clock and reset inputs.

The reset is active low, and independent of the clock.

http://onsemi.com

• Static Operation

• All Inputs and Outputs Buffered

• Diode Protection on All Inputs

MARKING

DIAGRAMS

PDIP–16

P SUFFIX

CASE 648

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

MC14174BCP

AWLYYWW

• Capable of Driving Two Low–Power TTL Loads or One Low–Power

Schottky TTL Load over the Rated Temperature Range

• Functional Equivalent to TTL 74174

SOIC–16

D SUFFIX

CASE 751B

14174B

AWLYWW

MAXIMUM RATINGS (Voltages Referenced to V ) (Note 2.)

Symbol

Parameter

Value

Unit

DC Supply Voltage Range

–0.5 to +18.0

SOEIAJ–16

F SUFFIX

CASE 966

MC14174B

ALYW

V , V

in out

Input or Output Voltage Range

(DC or Transient)

–0.5 to V + 0.5

I , I

Input or Output Current

(DC or Transient) per Pin

±10

in out

WL, L

YY, Y

= Assembly Location

= Wafer Lot

Power Dissipation,

per Package (Note 3.)

500

= Year

WW, W = Work Week

Ambient Temperature Range

Storage Temperature Range

–55 to +125

–65 to +150

260

°C

stg

ORDERING INFORMATION

Lead Temperature

(8–Second Soldering)

Device

Package

PDIP–16

SOIC–16

Shipping

2. Maximum Ratings are those values beyond which damage to the device

may occur.

3. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

MC14174BCP

MC14174BD

2000/Box

48/Rail

MC14174BDR2

SOIC–16 2500/Tape & Reel

MC14174BF

SOEIAJ–16

See Note 1.

high–impedance circuit. For proper operation, V and V should be constrained

out

MC14174BFEL

to the range V v (V or V ) v V

out

1. For ordering information on the EIAJ version of

the SOIC packages, please contact your local

ON Semiconductor representative.

Unused inputs must always be tied to an appropriate logic voltage level (e.g.,

either V or V ). Unused outputs must be left open.

Semiconductor Components Industries, LLC, 2000

Publication Order Number:

August, 2000 – Rev. 4

MC14174B/D

12 3 4 5 6 7 8

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