Datasheet > 1338BC-31SRI

1338BC-31SRI

更新时间： 2024-02-23 04:30:25

品牌	Logo	应用领域
艾迪悌 - IDT		光电二极管外围集成电路
页数	文件大小	规格书
23页	427K
描述
Real Time Clock, Non-Volatile, 1 Timer(s), PDSO16, 0.300 INCH, ROHS COMPLIANT, SOIC-16

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技术参数
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1338BC-31SRI 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SOIC
包装说明：	SOP, SOP16,.4	针数：	16
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.07
信息访问方法：	I2C	中断能力：	N
JESD-30 代码：	R-PDSO-G16	JESD-609代码：	e3
长度：	10.3 mm	湿度敏感等级：	1
端子数量：	16	计时器数量：	1
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP16,.4	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	峰值回流温度（摄氏度）：	260
电源：	3.3 V	认证状态：	Not Qualified
座面最大高度：	2.65 mm	子类别：	Timer or RTC
最大供电电压：	5.5 V	最小供电电压：	2.45 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn) - annealed	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
最短时间：	SECONDS	处于峰值回流温度下的最长时间：	30
易失性：	NO	宽度：	7.5 mm
uPs/uCs/外围集成电路类型：	TIMER, REAL TIME CLOCK	Base Number Matches：	1

1338BC-31SRI 数据手册

IDT1338B-31

REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM

RTC

Data Transfer on I C Serial Bus

Depending upon the state of the R/W bit, two types of data

transfer are possible:

bit (see the “Data Write–Slave Receiver Mode” figure). The

slave address byte is the first byte received after the START

condition is generated by the master. The slave address

byte contains the 7-bit IDT1338B-31 address, which is

1101000, followed by the direction bit (R/W), which is 0 for a

write. After receiving and decoding the slave address byte

the slave outputs an acknowledge on the SDA line. After the

IDT1338B-31 acknowledges the slave address + write bit,

the master transmits a register address to the IDT1338B-31.

This sets the register pointer on the IDT1338B-31, with the

IDT1338B-31 acknowledging the transfer. The master may

then transmit zero or more bytes of data, with the

1) Data transfer from a master transmitter to a slave

receiver. The first byte transmitted by the master is the

slave address. Next follows a number of data bytes. The

slave returns an acknowledge bit after each received byte.

Data is transferred with the most significant bit (MSB) first.

2) Data transfer from a slave transmitter to a master

receiver. The first byte (the slave address) is transmitted by

the master. The slave then returns an acknowledge bit. This

is followed by the slave transmitting a number of data bytes.

The master returns an acknowledge bit after all received

bytes other than the last byte. At the end of the last received

byte, a “not acknowledge” is returned. The master device

generates all of the serial clock pulses and the START and

STOP conditions. A transfer is ended with a STOP condition

or with a repeated START condition. Since a repeated

START condition is also the beginning of the next serial

transfer, the bus is not released. Data is transferred with the

most significant bit (MSB) first.

IDT1338B-31 acknowledging each byte received. The

address pointer increments after each data byte is

transferred. The master generates a STOP condition to

terminate the data write.

2) Slave Transmitter Mode (Read Mode): The first byte is

received and handled as in the slave receiver mode.

However, in this mode, the direction bit indicates that the

transfer direction is reversed. Serial data is transmitted on

SDA by the IDT1338B-31 while the serial clock is input on

SCL. START and STOP conditions are recognized as the

beginning and end of a serial transfer (see the “Data

Read–Slave Transmitter Mode” figure). The slave address

byte is the first byte received after the START condition is

generated by the master. The slave address byte contains

the 7-bit IDT1338B-31 address, which is 1101000, followed

by the direction bit (R/W), which is 1 for a read. After

receiving and decoding the slave address byte the slave

outputs an acknowledge on the SDA line. The IDT1338B-31

The IDT1338B-31 can operate in the following two modes:

1) Slave Receiver Mode (Write Mode): Serial data and

clock are received through SDA and SCL. After each byte is

received an acknowledge bit is transmitted. START and

STOP conditions are recognized as the beginning and end

of a serial transfer. Address recognition is performed by

hardware after reception of the slave address and direction

IDT™ REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 9

IDT1338B-31 REV A 112309

1...6 7 8910 11 12...23

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与1338BC-31SRI相关器件

型号	品牌	描述	获取价格	数据表
1338BC-31SRI8	IDT	Real Time Clock, Non-Volatile, 1 Timer(s), PDSO16, 0.300 INCH, ROHS COMPLIANT, SOIC-16	获取价格
1338C-18SRI	IDT	REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM	获取价格
1338C-18SRI8	IDT	REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM	获取价格
1338C-31SRI	IDT	REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM	获取价格
1338C-31SRI8	IDT	REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM	获取价格
1338G0	ETC	Peripheral IC	获取价格

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