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11575-811

更新时间： 2024-01-27 15:53:53
品牌 Logo 应用领域
其他 - ETC 晶体时钟发生器外围集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
25页 1413K
描述
EEPROM Programmable 3-PLL Clock Generator IC

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11575-811 技术参数

生命周期：Transferred包装说明：0.150 INCH, SOIC-16
Reach Compliance Code：unknown风险等级：5.77
Is Samacsys：N其他特性：OPERATES AT 3.3V MINIMUM SUPPLY
JESD-30 代码：R-PDSO-G16长度：9.89 mm
端子数量：16最高工作温度：70 °C
最低工作温度：最大输出时钟频率：150 MHz
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
主时钟/晶体标称频率：27 MHz认证状态：Not Qualified
座面最大高度：1.73 mm最大供电电压：5.5 V
最小供电电压：4.5 V标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
宽度：3.9 mmuPs/uCs/外围集成电路类型：CLOCK GENERATOR, OTHER
Base Number Matches：1

11575-811 数据手册

 浏览型号11575-811的Datasheet PDF文件第7页浏览型号11575-811的Datasheet PDF文件第8页浏览型号11575-811的Datasheet PDF文件第9页浏览型号11575-811的Datasheet PDF文件第11页浏览型号11575-811的Datasheet PDF文件第12页浏览型号11575-811的Datasheet PDF文件第13页 
FS6370-01  
EEPROM Programmable 3-PLL Clock Generator IC  
9.0 Programming Information  
Table 3: Register Map (Note: All Register Bits are cleared to zero on power-up.)  
ADDRESS  
BIT 7  
BIT 6  
BIT 5  
BIT 4  
BIT 3  
BIT 2  
BIT 1  
BIT 0  
MUX_D2[1:0]  
MUX_C2[1:0]  
BYTE 15  
PDPOST_D  
PDPOST_C  
PDPOST_B  
PDPOST_A  
(selected via SEL_CD = 1)  
(selected via SEL_CD = 1)  
POST_D2[3:0]  
POST_C2[3:0]  
BYTE 14  
(selected via SEL_CD = 1)  
(selected via SEL_CD = 1)  
POST_D1[3:0]  
POST_C1[3:0]  
BYTE 13  
BYTE 12  
BYTE 11  
(selected via SEL_CD = 0)  
(selected via SEL_CD = 0)  
POST_B[3:0]  
POST_A[3:0]  
MUX_D1[1:0]  
(selected via SEL_CD = 0)  
LFTC_C2  
CP_C2  
FBKDIV_C2[10:8] M-Counter  
Reserved (0)  
(SEL_CD=1)  
(SEL_CD=1)  
(selected via SEL_CD pin = 1)  
FBKDIV_C2[7:3] M-Counter  
FBKDIV_C2[2:0] A-Counter  
BYTE 10  
BYTE 9  
BYTE 8  
BYTE 7  
BYTE 6  
(selected via SEL_CD pin = 1)  
(selected via SEL_CD pin = 1)  
REFDIV_C2[7:0]  
(selected via SEL_CD pin = 1)  
MUX_C1[1:0]  
LFTC_C1  
CP_C1  
FBKDIV_C1[10:8] M-Counter  
PDPLL_C  
(selected via SEL_CD = 0)  
(SEL_CD=0)  
(SEL_CD=0)  
(selected via SEL_CD = 0)  
FBKDIV_C1[7:3] M-Counter  
FBKDIV_C1[2:0] A-Counter  
(selected via SEL_CD = 0)  
(selected via SEL_CD = 1)  
REFDIV_C1[7:0]  
(selected via SEL_CD = 0)  
BYTE 5  
BYTE 4  
BYTE 3  
BYTE 2  
BYTE 1  
BYTE 0  
MUX_B[1:0]  
MUX_A[1:0]  
PDPLL_B  
FBKDIV_B[7:3] M-Counter  
LFTC_B CP_B  
FBKDIV_B[10:8] M-Counter  
FBKDIV_B[2:0] A-Counter  
REFDIV_B[7:0]  
LFTC_A CP_A  
PDPLL_A  
FBKDIV_A[7:3] M-Counter  
FBKDIV_A[10:8] M-Counter  
FBKDIV_A[2:0] A-Counter  
REFDIV_A[7:0]  
If the power-down bit contains a zero, the related circuit  
will continue to function regardless of the PD pin state.  
9.1  
Control Bit Assignments  
If any PLL control bit is altered during device operation,  
including those bits controlling the Reference and Feed-  
back Dividers, the output frequency will slew smoothly (in  
a glitch-free manner) to the new frequency. The slew rate  
is related to the programmed loop filter time constant.  
However, any programming changes to any Mux or Post  
Divider control bits will cause a glitch on an operating  
clock output.  
Table 4: Power-Down Bits  
NAME  
DESCRIPTION  
Power-Down PLL A  
PDPLL_A  
(Bit 21)  
Bit = 0  
Bit = 1  
Power On  
Power Off  
Power-Down PLL B  
PDPLL_B  
(Bit 45)  
Bit = 0  
Bit = 1  
Power On  
Power Off  
9.1.1 Power Down  
All power-down functions are controlled by enable bits.  
That is, the bits select which portions of the FS6370 to  
power-down when the PD input is asserted. If the power-  
down bit contains a one, the related circuit will shut down  
if the PD pin is high (Run Mode only). When the PD pin is  
low, power is enabled to all circuits.  
Power-Down PLL C  
PDPLL_C  
(Bit 69)  
Bit = 0  
Bit = 1  
Power On  
Power Off  
Reserved (0)  
(Bit 69)  
Set these reserved bits to zero (0)  
10  
1...78910111213...25

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