Datasheet > 11575-811

11575-811

更新时间： 2024-01-05 18:22:47

品牌	Logo	应用领域
其他 - ETC		晶体时钟发生器外围集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
25页	1413K
描述
EEPROM Programmable 3-PLL Clock Generator IC

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11575-811 技术参数

生命周期：	Transferred	包装说明：	0.150 INCH, SOIC-16
Reach Compliance Code：	unknown	风险等级：	5.77
Is Samacsys：	N	其他特性：	OPERATES AT 3.3V MINIMUM SUPPLY
JESD-30 代码：	R-PDSO-G16	长度：	9.89 mm
端子数量：	16	最高工作温度：	70 °C
最低工作温度：		最大输出时钟频率：	150 MHz
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
主时钟/晶体标称频率：	27 MHz	认证状态：	Not Qualified
座面最大高度：	1.73 mm	最大供电电压：	5.5 V
最小供电电压：	4.5 V	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
宽度：	3.9 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER
Base Number Matches：	1

11575-811 数据手册

FS6370-01

EEPROM Programmable 3-PLL Clock Generator IC

bytes transferred between START and STOP conditions

is determined by the master device, and can continue

indefinitely. However, data that is overwritten to the de-

8.0 I²C-bus Control Interface

This device is a read/write slave device

vice after the first sixteen bytes will overflow into the first

overwritten fashion.

meeting all Philips I²C-bus specifications

except a “general call.” The bus has to be

controlled by a master device that generates

the serial clock SCL, controls bus access, and generates

the START and STOP conditions while the device works

as a slave. Both master and slave can operate as a

transmitter or receiver, but the master device determines

which mode is activated. A device that sends data onto

the bus is defined as the transmitter, and a device re-

ceiving data as the receiver.

8.1.5 Acknowledge

When addressed, the receiving device is required to gen-

erate an Acknowledge after each byte is received. The

master device must generate an extra clock pulse to co-

incide with the Acknowledge bit. The acknowledging de-

vice must pull the SDA line low during the high period of

the master acknowledge clock pulse. Setup and hold

times must be taken into account.

The master must signal an end of data to the slave by not

generating and acknowledge bit on the last byte that has

been read (clocked) out of the slave. In this case, the

slave must leave the SDA line high to enable the master

to generate a STOP condition.

I²C-bus logic levels noted herein are based on a percent-

age of the power supply (V_DD). A logic-one corresponds

to a nominal voltage of V_DD, while a logic-low corre-

sponds to ground (V_SS).

8.1

Bus Conditions

Data transfer on the bus can only be initiated when the

bus is not busy. During the data transfer, the data line

(SDA) must remain stable whenever the clock line (SCL)

is high. Changes in the data line while the clock line is

high will be interpreted by the device as a START or

STOP condition. The following bus conditions are defined

by the I²C-bus protocol.

8.2

I²C-bus Operation

All programmable registers can be accessed randomly or

sequentially via this bi-directional two wire digital inter-

face. The device accepts the following I²C-bus com-

mands.

8.2.1 Device Address

8.1.1 Not Busy

After generating a START condition, the bus master

Both the data (SDA) and clock (SCL) lines remain high to

indicate the bus is not busy.

broadcasts a seven-bit device address followed by a R/W

bit.

The device address of the FS6370 is:

8.1.2 START Data Transfer

A high to low transition of the SDA line while the SCL in-

put is high indicates a START condition. All commands to

the device must be preceded by a START condition.

Any one of eight possible addresses are available for the

EEPROM. The least significant three bits are don’t care’s.

8.1.3 STOP Data Transfer

A low to high transition of the SDA line while SCL is held

high indicates a STOP condition. All commands to the

device must be followed by a STOP condition.

8.1.4 Data Valid

The state of the SDA line represents valid data if the SDA

line is stable for the duration of the high period of the SCL

line after a START condition occurs. The data on the

SDA line must be changed only during the low period of

the SCL signal. There is one clock pulse per data bit.

Each data transfer is initiated by a START condition and

terminated with a STOP condition. The number of data

1...4 5 678 9 10...25

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