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11565-811 PDF预览

11565-811

更新时间: 2024-12-01 03:53:07
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其他 - ETC 晶体时钟发生器外围集成电路光电二极管
页数 文件大小 规格书
17页 210K
描述
Motherboard Clock Generator IC

11565-811 数据手册

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0RWKHUERDUGꢅ&ORFNꢅ*HQHUDWRUꢅ,&  
January 2000  
1.0 Features  
2.0 Description  
Generates clocks required for Intel® i820 based  
desktop and workstation systems, including:  
The FS6261-01 is a CMOS clock generator IC designed  
for high-speed motherboard applications. Two different  
frequencies can be selected for the CPU clocks via two  
SEL pins. Glitch-free stop clock control of the CPU, AGP  
(66MHz) and PCI clocks is provided. A low current  
power-down mode is available for mobile applications.  
Separate clock buffers provide for a 2.5V voltage range  
on the CPU_0:3, CPU/2_0:1 and APIC_0:2 clocks.  
Four enabled 2.5V 133/100MHz CPU Front Side  
Bus (FSB) clocks  
Two 2.5V CPU/2 clocks for synchronous memory  
Seven enabled 3.3V PCI bus clocks and one  
free-running PCI clock  
Four enabled 3.3V 66MHz AGP clocks  
Three 2.5V 16.67MHz APIC bus clocks  
Two 3.3V 14.318MHz REF clocks  
One 3.3V 48MHz USB clock  
Figure 2: Pin Configuration  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
VSS_R  
REF_0  
REF_1  
VDD_R  
VDD_A  
APIC_2  
APIC_1  
APIC_0  
VSS_A  
VDD_C2  
CPU/2_1  
CPU/2_0  
VSS_C2  
VDD_C  
CPU_3  
CPU_2  
VSS_C  
VDD_C  
CPU_1  
CPU_0  
VSS_C  
VDD  
2
3
CPU clock cycle – cycle jitter < 150ps p-p  
4
5
XIN  
Non-linear spread-spectrum modulation  
(-0.5% at 31.5kHz)  
6
XOUT  
7
VSS_P  
2(.  
5
V
8
PCI_F  
PCI_1  
Supports test mode and tristate output control  
uot  
9
upt  
Separate CPU-enable, PCI-enable and power-down  
inputs with glitch-free stop clock controls on all clocks  
for clock control and power management  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
VDD_P  
PCI_2  
s
)
F
PCI_3  
2S-601  
VSS_P  
PCI_4  
PCI_5  
Figure 1: Block Diagram  
VDD_P  
PCI_6  
XIN  
Crystal  
Oscillator  
PCI_7  
XOUT  
VDD_R  
VSS_P  
VSS_66  
CK66_0  
CK66_1  
VDD_66  
VSS_66  
CK66_2  
CK66_3  
VDD_66  
SEL133/100#  
VSS  
REF_0:1  
VSS_R  
PCI_STOP#  
CPU_STOP#  
PWR_DWN#  
SS_EN#  
SEL_1  
SEL_0:1  
SS_EN#  
PLL  
VDD_C2  
SEL_133/100#  
÷2  
CPU/2_0:1  
VSS_C2  
SEL_0  
VDD_A  
÷6 or  
÷8  
VDD_48  
CK48  
delay  
APIC_0:2  
VSS_A  
PWR_DWN#  
CPU_STOP#  
VSS_48  
VDD_C  
CPU_0:3  
VSS_C  
56-pin SSOP  
(2.5V outputs)  
VDD_66  
Table 1: CPU/PCI Frequency Selection  
÷1½  
or ÷2  
delay  
CK66_0:3  
VSS_66  
SEL_133/100#  
SEL_1  
SEL_0  
CPU (MHz)  
PCI (MHz)  
VDD_P  
÷3 or  
÷4  
delay  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
tristate  
(reserved)  
100  
tristate  
(reserved)  
33.33  
PCI_F  
PCI_1:7  
PCI_STOP#  
VSS_P  
100  
33.33  
VDD_48  
CK48  
÷3 or  
÷4  
PLL  
XIN/2  
XIN/6  
VSS_48  
(reserved)  
133  
(reserved)  
33.33  
FS6261-01  
133  
33.33  
Intel and Pentium are registered trademarks of Intel Corporation. Spread spectrum modulation is licensed under US Patent No. 5488627, Lexmark International, Inc. American Microsystems, Inc.  
reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  
1.31.00  
,62ꢀꢁꢁꢂ  

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