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10M50SAE144I7G

更新时间： 2024-02-25 12:33:38
品牌 Logo 应用领域
英特尔 - INTEL 时钟栅可编程逻辑
页数 文件大小 规格书
14页 604K
描述
Field Programmable Gate Array, PQFP144, 22 X 22 MM, 0.50 MM PITCH, ROHS COMPLIANT, PLASTIC, EQFP-144

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10M50SAE144I7G 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：HLFQFP, QFP144,.87SQ,20Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：1.52
Samacsys Description：FPGA - Field Programmable Gate Array其他特性：OPERATES AT 3.3V NOMINAL VCC
最大时钟频率：416 MHzJESD-30 代码：S-PQFP-G144
长度：20 mm湿度敏感等级：3
可配置逻辑块数量：3125输入次数：101
逻辑单元数量：50000输出次数：101
端子数量：144最高工作温度：100 °C
最低工作温度：-40 °C组织：3125, CLBS
封装主体材料：PLASTIC/EPOXY封装代码：HLFQFP
封装等效代码：QFP144,.87SQ,20封装形状：SQUARE
封装形式：FLATPACK, HEAT SINK/SLUG, LOW PROFILE, FINE PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY座面最大高度：1.65 mm
最大供电电压：3.15 V最小供电电压：2.85 V
标称供电电压：3 V表面贴装：YES
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：20 mm
Base Number Matches：1

10M50SAE144I7G 数据手册

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M10-OVERVIEW  
2014.09.22  
10  
User Flash Memory  
Feature  
Description  
Up to 17 single-ended external inputs for  
single ADC devices  
One dedicated analog and 16 dual function input pins  
Up to 18 single-ended external inputs for  
dual ADC devices  
•
•
One dedicated analog and eight dual function input pins  
in each ADC block  
Simultaneous measurement capability for dual ADC  
devices  
On-chip temperature sensor  
Monitors external temperature data input with a sampling  
rate of up to 50 kilosamples per second  
User Flash Memory  
The user flash memory (UFM) block in MAX 10 devices stores non-volatile information.  
The UFM provides an ideal storage solution that you can access using the following protocols:  
•
•
Avalon Memory Mapped (Avalon-MM) slave interface to UFM  
SPI slave interface through Avalon-MM to UFM (available in version 14.1 of the Quartus II software  
onwards)  
Table 9: UFM Features  
Features  
Capacity  
Up to 10,000 times read and write cycle counts  
Maximum 116 MHz  
Endurance  
Operating frequency  
Data length storage  
Up to 32-bit length  
Embedded Multipliers and Digital Signal Processing Support  
MAX 10 devices support up to 144 embedded multiplier blocks. Each block supports one individual  
18 × 18-bit multiplier or two individual 9 × 9-bit multipliers.  
In addition to embedded multipliers, the MAX 10 device includes a combination of on-chip resources and  
external interfaces to increase performance, reduce system cost, and lower the power consumption of  
digital signal processing (DSP) systems. You can use the MAX 10 device on its own or as a DSP device co-  
processor to improve price-to-performance ratios of DSP systems.  
You can control the operation of the embedded multiplier blocks using the following options:  
•
•
Parameterize relevant IP cores with the Quartus II parameter editor  
Infer the multipliers directly with VHDL or Verilog  
System design features provided for MAX 10 devices:  
MAX 10 FPGA Device Overview  
Send Feedback  
Altera Corporation  
1...7891011121314

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