5秒后页面跳转
10AX032E3F27E2LG PDF预览

10AX032E3F27E2LG

更新时间: 2024-02-21 14:45:05
品牌 Logo 应用领域
英特尔 - INTEL 可编程逻辑
页数 文件大小 规格书
110页 1391K
描述
Field Programmable Gate Array, 320000-Cell, CMOS, PBGA672, 27 X 27 MM, ROHS COMPLIANT, FBGA-672

10AX032E3F27E2LG 技术参数

是否Rohs认证:符合生命周期:Active
包装说明:27 X 27 MM, ROHS COMPLIANT, FBGA-672Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.38
Is Samacsys:NJESD-30 代码:S-PBGA-B672
长度:27 mm输入次数:240
逻辑单元数量:320000输出次数:240
端子数量:672最高工作温度:100 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA672,26X26,40
封装形状:SQUARE封装形式:GRID ARRAY
峰值回流温度(摄氏度):NOT SPECIFIED电源:0.9 V
可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY认证状态:Not Qualified
座面最大高度:3.25 mm子类别:Field Programmable Gate Arrays
最大供电电压:0.93 V最小供电电压:0.87 V
标称供电电压:0.9 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:27 mmBase Number Matches:1

10AX032E3F27E2LG 数据手册

 浏览型号10AX032E3F27E2LG的Datasheet PDF文件第103页浏览型号10AX032E3F27E2LG的Datasheet PDF文件第104页浏览型号10AX032E3F27E2LG的Datasheet PDF文件第105页浏览型号10AX032E3F27E2LG的Datasheet PDF文件第107页浏览型号10AX032E3F27E2LG的Datasheet PDF文件第108页浏览型号10AX032E3F27E2LG的Datasheet PDF文件第109页 
A10-DATASHEET  
2015.12.31  
106  
Document Revision History  
Date  
Version  
Changes  
Made the following changes to the "Transceiver Performance for Arria 10 GT Devices" section.  
Added TX minimum data rate to the "Transmitter and Receiver Data Rate Performance" table.  
Changed the maximum data rate condition for chip-to-chip and backplane in the "Transmitter and  
Receiver Data Rate Performance" table.  
Changed the minimum frequency in the "ATX PLL Performance" table.  
Changed the minimum frequency in the "Fractional PLL Performance" table.  
Changed the minimum frequency in the "CMU PLL Performance" table.  
Added voltage condition to the maximum peak-to-peak diff p-p after configuration and to the VICM specifi‐  
cations in the "Receiver Specifications" table.  
Changed the voltage conditions for VOCM in the "Transmitter Specifications" table.  
Changed the VOD/VCCT Ratios in the "Typical Transmitter VOD Settings" table.  
Added the "Transceiver Clock Network Maximum Data Rate Specifications" table.  
January 2015  
2015.01.23  
Added a note in the "Transceiver Power Supply Operating Conditions" section.  
Made the following changes to the "Reference Clock Specifications" table:  
Added the input reference clock frequency parameters for the CMU PLL, ATX PLL, and fPLL PLL.  
Changed the maximum specification for rise time and fall time.  
Added the VICM (AC and DC coupled) parameters.  
Changed the maximum value for Transmitter REFCLK Phase Noise (622 MHz) when ≥ 1 MHz.  
Changed the Min, Typ, and Max values for the reconfig_clksignal in the "Transceiver Clocks Specifica‐  
tions" table.  
Made the following changes to the "Receiver Specifications" table:  
Added the maximum peak-to-peak differential input voltage after device configuration specifications.  
Changed the minimum specification for the minimum differential eye opening at receiver serial input  
pins parameter.  
Removed the 120-ohm and 150-ohm conditions for the differential on-chip termination resistors  
parameter.  
Added the VICM (AC and DC coupled) parameter.  
Added the Programmable DC Gain parameter.  
Arria 10 Device Datasheet  
Send Feedback  
Altera Corporation  

与10AX032E3F27E2LG相关器件

型号 品牌 描述 获取价格 数据表
10AX032E3F27I2SG INTEL Field Programmable Gate Array, 320000-Cell, CMOS, PBGA672, 27 X 27 MM, ROHS COMPLIANT, FBG

获取价格

10AX032E3F29E2SG INTEL Field Programmable Gate Array, 320000-Cell, CMOS, PBGA780, 29 X 29 MM, ROHS COMPLIANT, FBG

获取价格

10AX032E3F29I2SG INTEL Field Programmable Gate Array, 320000-Cell, CMOS, PBGA780, 29 X 29 MM, ROHS COMPLIANT, FBG

获取价格

10AX032E4F29I3LG INTEL Field Programmable Gate Array, 320000-Cell, CMOS, PBGA780, 29 X 29 MM, ROHS COMPLIANT, FBG

获取价格

10AX032H2F34I2SG INTEL Field Programmable Gate Array, 320000-Cell, CMOS, PBGA1152, 35 X 35 MM, ROHS COMPLIANT, FB

获取价格

10AX032H3F34E2SG INTEL Field Programmable Gate Array, 320000-Cell, CMOS, PBGA1152, 35 X 35 MM, ROHS COMPLIANT, FB

获取价格