100398QIX

更新时间： 2024-01-30 20:51:45

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		转换器锁存器接口集成电路
页数	文件大小	规格书
13页	120K
描述
ECL-to-TTL Translator

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技术参数
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100398QIX 技术参数

生命周期：	Contact Manufacturer	包装说明：	QCCJ,
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.78
最大延迟：	5.8 ns	接口集成电路类型：	TTL TO ECL TRANSCEIVER
JESD-30 代码：	S-PQCC-J28	长度：	11.43 mm
位数：	1	功能数量：	4
端子数量：	28	最高工作温度：	85 °C
最低工作温度：	-40 °C	输出特性：	3-STATE
输出锁存器或寄存器：	LATCH	输出极性：	COMPLEMENTARY
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
座面最大高度：	4.57 mm	最大供电电压：	5.5 V
最小供电电压：	4.5 V	标称供电电压：	5 V
表面贴装：	YES	技术：	ECL
温度等级：	INDUSTRIAL	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
宽度：	11.43 mm	Base Number Matches：	1

100398QIX 数据手册

February 1992

Revised August 2000

100398

Quad Differential ECL/TTL Translating Transceiver

with Latch

General Description

Features

■ Differential ECL input/output structure

The 100398 is a quad latched transceiver designed to con-

vert TTL logic levels to differential F100K ECL logic levels

and vice versa. This device was designed with the capabil-

ity of driving a differential 25Ω ECL load with cutoff capabil-

ity, and will sink a 64 mA TTL load. The 100398 is ideal for

mixed technology applications utilizing either an ECL or

TTL backplane.

■ 64 mA FAST TTL outputs

■ 25Ω differential ECL outputs with cut-off

■ Bi-directional translation

■ 2000V ESD protection

■ Latched outputs

The direction of translation is set by the direction control

pin (DIR). The DIR pin on the 100398 accepts TTL logic

levels. A TTL LOW on DIR sets up the ECL pins as inputs

and TTL pins as outputs. A TTL HIGH on DIR sets up the

TTL pins as inputs and ECL pins as outputs.

■ 3-STATE outputs

■ Voltage compensated operating range = −4.2V to −5.7V

A LOW on the output enable input pin (OE) holds the ECL

output in a cut-off state and the TTL outputs at a high

impedance level. A HIGH on the latch enable input (LE)

latches the data at both inputs even though only one output

is enabled at the time. A LOW on LE makes the latch trans-

parent.

The cut-off state is designed to be more negative than a

normal ECL LOW level. This allows the output emitter-fol-

lowers to turn off when the termination supply is −2.0V, pre-

senting a high impedance to the data bus. This high

impedance reduces termination power and prevents loss of

low state noise margin when several loads share the bus.

The 100398 is designed with FAST TTL output buffers,

featuring optimal DC drive and capable of quickly charging

and discharging highly capacitive loads. All Inputs have

50 kΩ pull-down resistors.

Ordering Code:

Order Number Package Number

Package Description

100398PC

100398QC

100398QI

N24E

V28A

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide

28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

Industrial Temperature Range (−40°C to +85°C)

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

FAST is a registered trademark of Fairchild Semiconductor.

DS010970

www.fairchildsemi.com

12 3 4 5 6 7...13

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