Enhanced PCI Bus Multimedia Controller (Low-Voltage)
Appendix B: MD207/MD208 - ZR36067-LV Interface
This appendix suggests the basic interconnection between the
ZR36067-LV and the MD207/208 video encoder. Naturally,
when these two devices are connected together there must be a
third device, mastering the YUV bus. Figure describes a basic
interconnection between the ZR36067-LV and the MD207/208,
with an arbitrary YUV source. This minimum example does not
use the graphics overlay capability of the MD207/208
Mapping the MD207/208 on the ZR36067-
LV’s GuestBus
The software driver must map the MD207/208 on the GuestBus.
The proper timing parameters (tdur = 12, trec = 15) of the MD207/
208 must be loaded to the GuestBus control register.
Reading/writing one byte from/to the MD207/208 requires two
GuestBus cycles: in the first cycle the address (index) of the
internal MD207/208 register is written, in the second one the
data byte is read/written. The RS (register select) input of the
MD207/208 is used to distinguish between the two types of
cycles. Connecting this pin to the ZR36067-LV’s GADR0 virtual-
ly creates two MD207/208 registers at the level of the GuestBus:
when GADR0 is low (even registers), the MD207/208 expects
address to be transferred on its D7:0 bus, when GADR0 is high
(odd registers) data is output or input on these lines. Another
way is to connect GADR2 to RS.
Other Guests
MD207A/208
V
ZR36067-LV
GCSn
DD
CS
RS
RD
GADR[0]
GRD
WR
D[7:0]
GWR
GDAT[7:0]
GPI/On
GPI/On
VCLKx2
VCLK
(Optional)
(Optional)
RESET
Test/Fldintr
VCLK
HSYNC
VSYNC
BLANK
YD[7:0]
CD[7:0]
HSYNC
VSYNC
(Optional)
Sync Polarity
Y[7:0]
U/V[7:0]
Since, unlike the ZR36067-LV, the sync polarity of the MD207/
208 is not programmable, then, depending on the YUV 4:2:2
source, it might be necessary to invert the HSYNC and VSYNC
of the MD207/208.
YUV 4:2:2 Source
Figure 16. ZR36067-LV - MD207/208 Basic Interconnection
Vertical Interpolation with the MD208
MD207/208 Reset
Pin 8 is the only one that is different between the MD207A and
the MD208. While in the MD207A it is a test pin, normally con-
nected to ground, the MD208 uses this input to switch its internal
vertical interpolation mechanism on and off. When this mecha-
nism is on, one field out of every pair is vertically interpolated
and the interpolated lines are the ones sent out. Since this oper-
ation is not always desired (e.g., in high resolution still pictures
of VideoCD 2.0) it must be controlled by the software. The
natural way to obtain this control is using one of the GPI/Os. It is
better to pull this pin down in order for the same layout to support
both the MD207A and the MD208.
Software controlled usage of the RESET input of the MD207/208
is optional. Generally, it is more efficient to connect it to the
power-up reset of the circuit, and control the device through the
software reset register bit of the MD207/208. If a hardware reset
is needed in the design, any of the software controlled GPI/O
pins (configured as output) of the ZR36067-LV may be used as
a RESET signal. The software then directly manipulates the
RESET signal through the corresponding register bit of the
ZR36067-LV. Since the default configuration of the GPI/O pins
after reset is input, a pull down resistor should be applied to the
MD207/208 RESET input.
47
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