Datasheet > ZM7332G-65508-T1

ZM7332G-65508-T1

更新时间： 2022-03-04 01:45:40

品牌	Logo	应用领域
POWER-ONE		/
页数	文件大小	规格书
33页	680K
描述
Digital Power Manager

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中文翻译

获取价格

数据手册

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ZM7332G-65508-T1 数据手册

ZM7300G Series Digital Power Manager

Data Sheet

8.4

I²C Interface

Parameter

Conditions/Description

Input low voltage

Min

-0.5

Nom

Max

Units

ViL

ViH

Vhys

VoL

t_r

0.3·VDD

VDD+0.5

Input high voltage

0.7·VDD

0.05·VDD

Input hysteresis

Output low voltage, I_SINK=3mA

Rise time for SDA and SCL

Output fall time from ViHmin to ViLmax

Input current each I/O pin, 0.1V_DD<V_i<0.9V_DD

Capacitance for each I/O pin

SCL clock frequency

0.4

300

250

20+0.1C_b

-10

μA

kHz

t_of

f_SCL

400

Standard-Mode I²C (f_SCL≤ 100kHz)

R_PU

t_HDSTA

t_LOW

External pull-up resistor

Hold time (repeated) START condition

Low period of the SCL clock

1000/C_b

kΩ

μs

4.0

4.7

4.0

4.7

t_HIGH

High period of the SCL clock

t_SUSTA

t_HDDAT

t_SUDAT

t_SUSTD

t_SUF

Setup time for a repeated START condition

Data hold time

3.45

Data setup time

250

4.0

4.7

Setup time for STOP condition

Bus free time between a STOP and START condition

Fast-Mode I²C (100kHz < f_SCL≤ 400kHz)

R_PU

t_HDSTA

t_LOW

External pull-up resistor

Hold time (repeated) START condition

Low period of the SCL clock

300/C_b

kΩ

μs

0.6

1.3

0.6

t_HIGH

High period of the SCL clock

t_SUSTA

t_HDDAT

t_SUDAT

t_SUSTD

t_SUF

Setup time for a repeated START condition

Data hold time

0.9

Data setup time

100

0.6

1.3

Setup time for STOP condition

Bus free time between a STOP and START condition

______________________________________

C_b– bus capacitance in pF, typically from 10pF to 400pF

t_o

t_HIG

t_LO

t_r

t_LO

SCL

SDA

t_SUST

t_HDST

t_HDDAt_SUDA

t_SUST

t_BU

Figure 2. I²C Timing Parameters

www.power-one.com

ZD-00896 Rev. 5.1, 13-Jul-10

Page 6 of 33

1...3 4 567 8 9...33

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