Datasheet > ZM7332G-65508-Q1

ZM7332G-65508-Q1

更新时间： 2022-12-18 03:22:55

品牌	Logo	应用领域
POWER-ONE		/
页数	文件大小	规格书
33页	680K
描述
Digital Power Manager

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数据手册

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ZM7332G-65508-Q1 数据手册

ZM7300G Series Digital Power Manager

Data Sheet

8.3

Signal Specifications

Parameter

Conditions/Description

SYNC/DATA Line

Min

Nom

Max

Units

SDpu

SDthrL

SDthrH

SDhys

SDsink

Freq_sd

SD pull up resistor

SD input low voltage threshold

SD input high voltage threshold

SD input hysteresis

kΩ

0.31·VDD

0.45·VDD

0.37

0.52·VDD

0.81·VDD

1.1

SD sink capability (V_SD=0.5V)

Clock frequency

kHz

% of clock

cycle

% of clock

cycle

450

550

Tsynq

Sync pulse duration

Data=0 pulse duration

Interrupt Inputs (INT_N[3:0])

Pull up resistor

Rpu3

VthrL3

VthrH3

Vhys3

kΩ

Input low voltage threshold

Input high voltage threshold

Input hysteresis

0.31·VDD

0.45·VDD

0.37

0.52·VDD

0.81·VDD

1.1

ADDR[3:0], ACFAIL_N, RES_N, LCK_N, PG[3:0] Inputs

Rpu1

VthrL1

VthrH1

Pull up resistor

Input low voltage

Input high voltage

-0.5

kΩ

0.2·VDD

VDD+0.5

0.7·VDD

HRES_N Input

HRES_N pull up resistor (with series

diode, see note 1)

Rpu2

kΩ

VthrL2

VthrH2

HRES_N input low voltage

HRES_N input high voltage

-0.5

0.2·VDD

VDD+0.5

0.9·VDD

Inputs/Outputs (OK_A, OK_B, OK_C, OK_D)

OKpu

OKthrL

OKthrH

OKhys

OKsink

OK pull up resistor

kΩ

OK input low voltage threshold

OK input high voltage threshold

OK input hysteresis

0.31·VDD

0.45·VDD

0.37

0.52·VDD

0.81·VDD

1.1

OK sink capability (V_OK=0.5V)

Enable Outputs (EN[3:0])

V_EN

EN logic level enabled

EN logic level disabled

High

Low

EN output high voltage

I_OH= -10 mA

EN output low voltage

I_OL= 5 mA

V_EN

VDD-0.6

V_EN

0.5

______________________________________

HRES_N Input - Because the input does not have an internal ESD protection diode connected to VDD, the user needs to add an external

diode between the HRES_N and VDD pins as shown in Figure 3.

ZD-00896 Rev. 5.1, 13-Jul-10

www.power-one.com

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