Datasheet > ZL50019GAG2

ZL50019GAG2

更新时间： 2024-01-22 21:55:36

品牌	Logo	应用领域
加拿大卓联 - ZARLINK		电信集成电路
页数	文件大小	规格书
121页	921K
描述
Enhanced 2 K Digital Switch with Stratum 4E DPLL

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ZL50019GAG2 技术参数

ZL50019

Data Sheet

Performance Characteristics Notes

† Characteristics are over recommended operating conditions unless otherwise stated.

‡ Typical figures are at 25°C, V_{DD_CORE}at 1.8 V and V_{DD_IO}at 3.3 V and are for design aid only: not guaranteed and not subject to production

testing.

1. Jitter on master clock input (XIN) is 100 ps pp or less.

2. Jitter on reference input (REF0-3) is 2 ns pp or less.

3. Normal Mode selected.

4. Holdover Mode selected.

5. Freerun Mode selected.

6. Jitter is measured without an output filter.

7. Accuracy of master clock input (XIN) is 0 ppm.

8. Accuracy of master clock input (XIN) is 100 ppm.

9. Capture range is +/-260 ppm; inaccuracy of XIN shifts this range.

10. Phase alignment speed (phase slope) is programmed to 7 ns/125µs.

11. Any input reference switch or state switch (i.e. REF0 to REF3, Normal to Holdover, etc.).

12. Multi-period near limits and far limits are programmed to +/-64.713 ppm & +/-82.487 ppm respectively. (ST4_LIM = 1)

13. Multi-period near limits and far limits are programmed to +/-240 ppm & +/-250 ppm respectively. (ST4_LIM = 0)

14. 30 pF load on output pin.

118

Zarlink Semiconductor Inc.

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