Datasheet > Z8018220AEG

Z8018220AEG

更新时间： 2022-09-29 19:10:31

品牌	Logo	应用领域
ZILOG		/
页数	文件大小	规格书
109页	821K
描述
IC MPU ZIP 20MHZ 100VQFP

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数据手册

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Z8018220AEG 数据手册

Z80182/Z8L182

ZILOG INTELLIGENT PERIPHERAL

Zilog

P R E L I M I N A R Y

GENERAL DESCRIPTION (Continued)

D7-D0

EV1

EV2

Control

GLU

Logic

A19-A0

Bus

Transceiver

Z8S180

(Static Z80180)

MPU Core

Tx Data

85230

ESCC

Channel

ESCC

Channel

Rx Data

ESCC

Control

/TRxCB

16550

MIMIC

Interface

/ROMCS

/RAMCS

Address

Decode

8-Bit Parallel

Port C

8-Bit Parallel

Port B

8-Bit Parallel

Port A

MUX

85230

ESCC Ch. A

or Port C

16550 MIMIC

or ESCC

85230 Ch. B

and PortA

Z180 Signals

or Port B

Note: Conventional use of the term "MPU side" refers to all interface through the Z180 MPU

core and "PC side" refers to all interface through the16550 MIMIC interface.

Figure 1. Z80182/Z8L182 Functional Block Diagram

DS971820600

3-2

PS009801-0301

123 4 5 6 7...109

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