Datasheet > Z8018216FSC

Z8018216FSC

更新时间： 2024-01-01 09:04:22

品牌	Logo	应用领域
ZILOG		时钟微控制器外围集成电路
页数	文件大小	规格书
109页	808K
描述
IC 8-BIT, 16 MHz, MICROCONTROLLER, PQFP100, PLASTIC, QFP-100, Microcontroller

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技术参数
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Z8018216FSC 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	QFP
包装说明：	PLASTIC, QFP-100	针数：	100
Reach Compliance Code：	not_compliant	HTS代码：	8542.31.00.01
风险等级：	5.33	位大小：	8
CPU系列：	Z80	最大时钟频率：	16 MHz
JESD-30 代码：	R-PQFP-G100	JESD-609代码：	e0
长度：	20 mm	I/O 线路数量：	24
端子数量：	100	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装等效代码：	QFP100,.7X.9
封装形状：	RECTANGULAR	封装形式：	FLATPACK
峰值回流温度（摄氏度）：	225	电源：	5 V
认证状态：	Not Qualified	RAM（字节）：
ROM（单词）：	0	座面最大高度：	3.1 mm
速度：	16 MHz	子类别：	Microcontrollers
最大压摆率：	100 mA	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	14 mm	uPs/uCs/外围集成电路类型：	MICROCONTROLLER
Base Number Matches：	1

Z8018216FSC 数据手册

Z80182/Z8L182

Zilog

ZILOG INTELLIGENT PERIPHERAL

P R E L I M I N A R Y

Z180 MPU DMA SIGNALS

/TEND0. Transfer End 0 (output, active Low). This output

is asserted active during the last write cycle of a DMA

operation. It is used to indicate the end of the block

transfer. /TEND0 is multiplexed with CKA1 on the

CKA1//TEND0 pin.

/DREQ0. DMA request 0 (input, active Low). /DREQ0 is

used to request a DMA transfer from DMA channel 0. The

DMA channel monitors the input to determine when an

external device is ready for a read or write operation. This

input can be programmed to be either level or edge

sensed. /DREQ0 is multiplexed with CKA0 on the

CKA0//DREQ0 pin.

/TEND1. Transfer End 1 (output, active Low). This output

is asserted active during the last write cycle of a DMA

operation. It is used to indicate the end of the block

transfer. /TEND1 is multiplexed with the ESCC signal

/RTSB and the 16550 MIMIC interface signal /HRxRDY on

the /TEND1//RTSB//HRxRDY pin.

/DREQ1. DMA request 1 (input, active Low). /DREQ1 is

used to request a DMA transfer from DMA channel 1. The

DMA channel monitors the input to determine when an

external device is ready for a read or write operation. This

input can be programmed to be either level or edge

sensed.

Z180^™MPU TIMER SIGNALS

T_OUT.Timer Out (output, active High). T_OUTis the pulse

output from PRT channel 1. This line is multiplexed with

A18 of the address bus on the A18/T_OUTpin.

Z85230 ESCC^™SIGNALS

TxDA. Transmit Data (output, active High). This output

signal transmits channel A’s serial data at standard TTL

levels. This output can be tri-stated during power down

modes.

control. /TRxCB may supply the receive clock or the

transmit clock in the input mode or supply the output of the

Digital Phase-Locked Loop (DPLL), the crystal oscillator,

the baud rate generator, or the transmit clock in output

mode. In Z80182/Z8L182 mode 1 /TRxCB is multiplexed

with the 16550 MIMIC interface HA0 input on the

/TRxCB/HA0 pin.

TxDB. Transmit Data (output, active High). This output

signal transmits channel B’s serial data at standard TTL

levels. In Z80182/Z8L182 mode 1, TxDB is multiplexed

with the 16550 MIMIC interface /HDDIS signal on the

TxDB//HDDIS pin.

/RTxCA. Receive/Transmit Clock (input, active Low). The

functions of this pin are under channel A program control.

In channel A, /RTxCA may supply the receive clock, the

transmit clock, the clock for the baud rate generator, or the

clock for the DPLL. This pin can also be programmed for

use by the /SYNCA pin as a crystal oscillator. The receive

clock may be 1, 16, 32, or 64 times the data rate in

asynchronous mode.

RxDA. Receive Data (inputs, active High). These inputs

receive channel A’s serial data at standard TTL levels.

RxDB. Receive Data (input, active High). These inputs

receive channel B’s serial data at standard TTL levels. In

Z80182/Z8L182 mode 1 RxDB is multiplexed with the

16550 MIMIC HA1 input on the RxDB/HA1 pin.

/RTxCB. Receive/Transmit Clock (input, active Low). The

functions of this pin are under channel B program control.

In channel B, /RTxCB may supply the receive clock, the

transmit clock, the clock for the baud rate generator, or the

clock for the DPLL. This pin can also be programmed for

use by the /SYNCB pin as a crystal oscillator. The receive

clock may be 1, 16, 32, or 64 times the data rate in

asynchronous mode. In Z80182/Z8L182 mode 1 the

/RTxCB signal is multiplexed with 16550 MIMIC interface

HA2 input on the /RTxCB/HA2 pin.

/TRxCA. Transmit/Receive Clock (input or output, active

Low). ThefunctionsofthispinareunderchannelAprogram

control. /TRxCA may supply the receive clock or the

transmit clock in the Input mode or supply the output of the

digital phase-locked loop, the crystal oscillator, the baud

rate generator, or the transmit clock in the output mode.

/TRxCB. Transmit/Receive Clock (input or output, active

Low). ThefunctionsofthispinareunderchannelBprogram

DS971820600

3-7

PS009801-0301

1...4 5 678 9 10...109

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