TDA4VH-Q1, TDA4AH-Q1, TDA4VP-Q1, TDA4AP-Q1
ZHCSRW2 –FEBRUARY 2023
www.ti.com.cn
3.1 Functional Block Diagram
图3-1 is functional block diagram for the device.
MAIN Domain
WKUP/MCU Domain
WKUP_SMS
M4F
AES
INTA
H.264/H.265
Encode/Decode
SECMGR
ROM 160K
WKUP_CTRL_MMR
WKUP_PSC
1× C71SS
1× C71SS
2× R5FSS
1× A72SS
WKUP_VTM
CTRL_MMR
DebugSS
WKUP_PLLCTRL
2×WKUP_GPIO
1×WKUP_I2C
1× C71x
1× C71x
DSP
2× Arm
2×Arm
WKUP_SA2SS
Cortex-A72
Cortex-R5F
DSP+MMA
MCU_SA2_UL
WKUP_DMSS_HSM
1×WKUP_UART
1×WKUP_ESM
PLLs
SecProxy/RA
AES3DES PKA
512KB L2
512KB L2
2MB L2
TCM 64KB
DBG
SHA
PSI-L PKTDMA
20×TIMER
10×WWDT
GPU BSX-64-4
MCU_CTRL_MMR
MSMC
MSMC
3×MCU_PLL
10×MCU_TIMER
2×MCU_WWDT
1024KB L3 RAM
DDRSS
2× 32b + in-line
ECC + MFLAG
ESM
1× DRU
+ CMMU
Compression
4MB SRAM with ECC
10× DCC
512B Scratchpad RAM
1× ATL
R5FSS
NAVSS
R5F
R5F
Spinlock
Channelized FW
2×TIMER_MGR
UDMA-P
VIRTSS
I-cache 32KB
I-cache 32KB
To CPSW
2×Mailbox
3×INTA
Proxy
D-cache 32KB
D-cache 32KB
2×PVU
CPTS
TCM 64KB
TCM 64KB
MCRC
RINGACC
MCU Internal Diagnostics
3x MCU_DCC 1×MCU_ESM
To MCU NAVSS
PSI-L
Local Interconnect
MCU NAVSS
2 x 512 KB SRAM
Interconnect
Channelized FW
INTA
INTR
RINGACC
UDMA-P
Proxy
MCRC
PSI-L
1×MCU_CPSW
To NAVSS
MCU_PDMA
2×MCU_I2C
1×MCU_I3C
3×MCU_MCSPI
1×MCU_UART
2×MCU_MCAN
2×OSPI
1×HPB
MCU_FSS
MUX
MUX
DPHY_RX
2×DPHY_TX
1×SERDES (4L)
2×MCU_ADC
(18ch/2b/4MSPS)
intro-001
图3-1. Functional Block Diagram
A. A solid black box indicates the IP is part of the Extended MCU (eMCU).
B. A dashed black box indicates that some instances of the IP are present in the eMCU and some instances are present in the non-eMCU
portion of the Main Domain.
Copyright © 2023 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: TDA4VH-Q1 TDA4AH-Q1 TDA4VP-Q1 TDA4AP-Q1
English Data Sheet: SPRSP79