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XR17V358IB176-F PDF预览

XR17V358IB176-F

更新时间： 2024-02-21 07:53:04
品牌 Logo 应用领域
艾科嘉 - EXAR PC
页数 文件大小 规格书
68页 1694K
描述
HIGH PERFORMANCE OCTAL PCI EXPRESS UART

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XR17V358IB176-F 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：LFBGA,Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.31.00.01
风险等级：1.66地址总线宽度：
边界扫描：YES总线兼容性：PCI
通信协议：ASYNC, BIT数据编码/解码方法：NRZ
最大数据传输速率：3.125 MBps外部数据总线宽度：8
JESD-30 代码：S-PBGA-B176JESD-609代码：e1
长度：13 mm低功率模式：YES
湿度敏感等级：4串行 I/O 数：8
端子数量：176最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：LFBGA封装形状：SQUARE
封装形式：GRID ARRAY, LOW PROFILE, FINE PITCH峰值回流温度（摄氏度）：245
认证状态：Not Qualified座面最大高度：1.5 mm
标称供电电压：1.2 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：0.8 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：13 mm
uPs/uCs/外围集成电路类型：SERIAL IO/COMMUNICATION CONTROLLER, SERIALBase Number Matches：1

XR17V358IB176-F 数据手册

 浏览型号XR17V358IB176-F的Datasheet PDF文件第4页浏览型号XR17V358IB176-F的Datasheet PDF文件第5页浏览型号XR17V358IB176-F的Datasheet PDF文件第6页浏览型号XR17V358IB176-F的Datasheet PDF文件第8页浏览型号XR17V358IB176-F的Datasheet PDF文件第9页浏览型号XR17V358IB176-F的Datasheet PDF文件第10页 
PRELIMINARY  
XR17V358  
REV. P1.0.2  
HIGH PERFORMANCE OCTAL PCI EXPRESS UART  
PIN DESCRIPTIONS  
NAME  
PIN #  
TYPE  
DESCRIPTION  
MPIO11  
M3  
I/O  
Multi-purpose input/output 11. The function of this pin is defined thru the Con-  
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.  
MPIO12  
MPIO13  
MPIO14  
MPIO15  
N2  
P2  
M4  
N3  
I/O  
I/O  
I/O  
I/O  
Multi-purpose input/output 12. The function of this pin is defined thru the Con-  
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.  
Multi-purpose input/output 13. The function of this pin is defined thru the Con-  
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.  
Multi-purpose input/output 14. The function of this pin is defined thru the Con-  
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.  
Multi-purpose input/output 15. The function of this pin is defined thru the Con-  
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.  
EEPROM SIGNALS  
EECK  
P13  
R14  
O
O
Serial clock to EEPROM. An internal clock of CLK divide by 256 is used for  
reading the vendor and sub-vendor ID during power up or reset. However, it  
can be manually clocked thru the Configuration Register REGB.  
EECS  
Chip select to a EEPROM device like 93C46. It is manually selectable thru  
the Configuration Register REGB. Requires a pull-up 4.7K ohm resistor for  
external sensing of EEPROM during power up.  
EEDI  
P14  
M12  
O
I
Write data to EEPROM device. It is manually accessible thru the Configura-  
tion Register REGB.  
EEDO  
Read data from EEPROM device. It is manually accessible thru the Configu-  
ration Register REGB.  
JTAG SIGNALS  
TRESET  
TCK  
N4  
P3  
M5  
R3  
P4  
I
I
JTAG Test Reset  
JTAG Test Clock  
TMS  
I
JTAG Test Mode Select  
JTAG Data Input  
TDI  
I
TDO  
O
JTAG Data Output  
BUCK REGULATOR SIGNALS  
ENABLE  
C14  
I
Connect to VCC to enable buck regulator. Connect to GND to disable buck  
regulator.  
LX  
LX  
A13  
A14  
O
O
Connect these two signals together to external 4.7uH inductor.  
FB  
C11  
I
Connect this signal to other end of external 4.7uH inductor. 47uF capacitor to  
GND is also required on this pin.  
PWRGD  
D13  
O
Indicates that 1.2V core has been powered up.  
ANCILLARY SIGNALS  
RESET#  
R2  
A10  
I
I
System reset (active low). In normal operation, this signal should be HIGH.  
16-bit timer/counter external clock input.  
TMRCK  
7
1...45678910...68

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