Datasheet > XPC860DTZP50D3

XPC860DTZP50D3

更新时间： 2024-02-07 08:32:59

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		/
页数	文件大小	规格书
76页	805K
描述
Family Hardware Specifications

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数据手册

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XPC860DTZP50D3 数据手册

Features

— Three parallel I/O registers with open-drain capability

• Four baud-rate generators (BRGs)

— Independent (can be connected to any SCC or SMC)

— Allow changes during operation

— Autobaud support option

• Four serial communications controllers (SCCs)

— Ethernet/IEEE 802.3 optional on SCC1–4, supporting full 10-Mbps operation

(available only on specially programmed devices).

— HDLC/SDLC (all channels supported at 2 Mbps)

— HDLC bus (implements an HDLC-based local area network (LAN))

— Asynchronous HDLC to support PPP (point-to-point protocol)

— AppleTalk

— Universal asynchronous receiver transmitter (UART)

— Synchronous UART

— Serial infrared (IrDA)

— Binary synchronous communication (BISYNC)

— Totally transparent (bit streams)

— Totally transparent (frame based with optional cyclic redundancy check (CRC))

• Two SMCs (serial management channels)

— UART

— Transparent

— General circuit interface (GCI) controller

— Can be connected to the time-division multiplexed (TDM) channels

• One SPI (serial peripheral interface)

— Supports master and slave modes

— Supports multimaster operation on the same bus

• One I²C (inter-integrated circuit) port

— Supports master and slave modes

— Multiple-master environment support

• Time-slot assigner (TSA)

— Allows SCCs and SMCs to run in multiplexed and/or non-multiplexed operation

— Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user

deﬁned

— 1- or 8-bit resolution

MOTOROLA

MPC860 Family Hardware Speciﬁcations

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