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XP2-40 PDF预览

XP2-40

更新时间: 2022-04-23 23:00:11
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莱迪思 - LATTICE /
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92页 1509K
描述
LatticeXP2 Family Data Sheet

XP2-40 数据手册

 浏览型号XP2-40的Datasheet PDF文件第1页浏览型号XP2-40的Datasheet PDF文件第3页浏览型号XP2-40的Datasheet PDF文件第4页浏览型号XP2-40的Datasheet PDF文件第5页浏览型号XP2-40的Datasheet PDF文件第6页浏览型号XP2-40的Datasheet PDF文件第7页 
LatticeXP2 Family Data Sheet  
Introduction  
February 2008  
Data Sheet DS1009  
Flexible I/O Buffer  
Features  
• sysIO™ buffer supports:  
flexiFLASH™ Architecture  
LVCMOS 33/25/18/15/12; LVTTL  
– SSTL 33/25/18 class I, II  
– HSTL15 class I; HSTL18 class I, II  
– PCI  
• Instant-on  
• Infinitely reconfigurable  
• Single chip  
• FlashBAK™ technology  
• Serial TAG memory  
LVDS, Bus-LVDS, MLVDS, LVPECL, RSDS  
Pre-engineered Source Synchronous  
Interfaces  
• Design security  
Live Update Technology  
• DDR / DDR2 interfaces up to 200 MHz  
• 7:1 LVDS interfaces support display applications  
• XGMII  
TransFR™ technology  
• Secure updates with 128 bit AES encryption  
• Dual-boot with external SPI  
sysDSP™ Block  
Density And Package Options  
• 5k to 40k LUT4s, 86 to 540 I/Os  
• Three to eight blocks for high performance  
Multiply and Accumulate  
• 12 to 32 18x18 multipliers  
• Each block supports one 36x36 multiplier or four  
18x18 or eight 9x9 multipliers  
• csBGA, TQFP, PQFP, ftBGA and fpBGA packages  
• Density migration supported  
Flexible Device Configuration  
• SPI (master and slave) Boot Flash Interface  
• Dual Boot Image supported  
Embedded and Distributed Memory  
• Soft Error Detect (SED) macro embedded  
• Up to 885 Kbits sysMEM™ EBR  
System Level Support  
• Up to 83 Kbits Distributed RAM  
• IEEE 1149.1 and IEEE 1532 Compliant  
• On-chip oscillator for initialization & general use  
• Devices operate with 1.2V power supply  
sysCLOCK™ PLLs  
• Up to four analog PLLs per device  
• Clock multiply, divide and phase shifting  
Table 1-1. LatticeXP2 Family Selection Guide  
Device  
XP2-5  
5
XP2-8  
8
XP2-17  
17  
XP2-30  
29  
XP2-40  
40  
LUTs (K)  
Distributed RAM (KBits)  
EBR SRAM (KBits)  
EBR SRAM Blocks  
sysDSP Blocks  
18 x 18 Multipliers  
10  
166  
9
18  
35  
56  
83  
221  
12  
276  
15  
387  
21  
885  
48  
3
4
5
7
8
12  
1.2  
2
16  
20  
28  
32  
V
Voltage  
1.2  
2
1.2  
4
1.2  
4
1.2  
4
CC  
GPLL  
Max Available I/O  
172  
201  
358  
472  
540  
Packages and I/O Combinations  
132-Ball csBGA (8 x 8 mm)  
144-Pin TQFP (20 x 20 mm)  
208-Pin PQFP (28 x 28 mm)  
256-Ball ftBGA (17 x17 mm)  
484-Ball fpBGA (23 x 23 mm)  
672-Ball fpBGA (27 x 27 mm)  
86  
86  
100  
146  
172  
100  
146  
201  
146  
201  
358  
201  
363  
472  
363  
540  
© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand  
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.  
www.latticesemi.com  
1-1  
DS1009 Introduction_01.2  

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