OPA3S2859-EP
ZHCSMS7B –APRIL 2021 –REVISED DECEMBER 2021
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表5-1. Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
Latch control input for Channel A. LTCH_A = logic high (default) = transparent mode, gain setting
changes based on SEL0 and SEL1 pins are reflected at the output.
LTCH_A = logic low = latch mode = changing SEL0 and SEL1 pins does not affect the gain
configuration of amplifier.
LTCH_A
3
I
Latch control input for Channel B. LTCH_B = logic high (default) = transparent mode, gain setting
changes based on SEL0 and SEL1 pins are reflected at the output.
LTCH_B = logic low = latch mode = changing SEL0 and SEL1 pins does not affect the gain
configuration of amplifier.
LTCH_B
4
I
PD
15
I
I
Power down pin. PD = logic high (default) = normal operation, PD = logic low = power down mode.
TIA gain selection. SEL0 = logic high (default). See 表5-2 for details.
TIA gain selection. SEL1 = logic high (default). See 表5-2 for details.
Output of amplifier A
SEL0
SEL1
VOUT_A
VOUT_B
VS-
5
2
I
19
O
O
I
12
Output of amplifier B
13, 18
14, 16, 17
Negative (lowest) power supply
VS+
I
Positive (highest) power supply
Connect the thermal pad to the most negative power supply (pin 13 and 18) of the device under test
(DUT).
Thermal pad
—
表5-2. Select Pin Decoder
SEL1
LOW
LOW
SEL0
HIGH
LOW
Gain
Low Gain, optimized for gain in < 10 kΩ range
Mid Gain, optimized for gain in 10 kΩ –100 kΩ
range
HIGH
LOW
High Gain, optimized for gain in > 100 kΩ range
HIGH (Default)
HIGH (Default)
External Gain. All internal switches open
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