MSPM0G1507, MSPM0G1506, MSPM0G1505
www.ti.com.cn
ZHCSRS3A – FEBRUARY 2023 – REVISED JUNE 2023
4 功能方框图
图 4-1 显示了 MSPM0G150x 功能框图。
PAx, PBx
tIOBUSt
ULPCLK
TX, RX,
UART3
CPU SUB SYSTEM
GPIO
CTS, RTS
Arm
Cortex-M0+
fmax = 80 MHz
SPI0
SPI1
POCI, PICO,
SCK, CSx
FLASH
Up to 128KB
NVIC
MPU
4-CH
FAULT
SRAM
Up to 32KB
TIMA0
TIMA1
SWD + MTB
IOPORT
DMA
7-ch
2-CH
FAULT
TIMG6
TIMG7
TRNG
MATHACL
2-CH
2-CH
TIMG12
32-bit
CPU-ONLY PD1 PERIPHERAL BUS (MCLK)
2-CH
WWDT0
WWDT1
IOMUX
CRC
AES
TEMP SENSOR
SWCLK,
SWDIO
12b ADC0
12b ADC1
A0_x
A1_x
DEBUG
RTC
FLASHCTL
ULPCLK
RTC_OUT
EVENT
VREF+,
VREF-
VREF
TX, RX,
CTS, RTS
UART0
OPA0
OPA1
IN+, IN-,
OUT
PMCU (SYSCTL)
TX, RX,
CTS, RTS
UART1
UART2
IN+, IN-,
OUT
CKM
PMU
LDO
GPAMP
I2C0
I2C1
SYSPLL
SDA, SCL
2-CH
LFOSC
SYSOSC
LFXT
BOR
POR
12b DAC0
DAC_OUT
TIMG0
TIMG8
COMP0
COMP1
COMP2
IN+, IN-,
OUT
VBOOST
2-CH
QEI/HALL
HFXT
Each COMPx includes an 8b
reference DAC; COMP0 and
COMP1 reference DACs connect
to OPA0 and OPA1, respectively
LEGEND
LFXIN, LFXOUT
HFXIN, HFXOUT
ROSC
VDD, VSS
VCORE, NRST
PD1, CPU ACCESS ONLY
PD1, CPU/DMA ACCESS
PD1/PD0, CPU/DMA ACCESS
PD0, CPU/DMA ACCESS
CLK_OUT, FCC_IN
图 4-1. MSPM0G150x 功能框图
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Product Folder Links: MSPM0G1507 MSPM0G1506 MSPM0G1505
English Data Sheet: SLASEW9