XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Features
• Safety for application
- Memory Protection Unit (MPU)
- Shared Memory Protection Unit (SMPU)
- Peripheral Protection Unit (PPU)
- Watchdog Timer (WDT)
- Multi-Counter Watchdog Timer (MCWDT)
- Low-Voltage Detector (LVD)
- Brown-Out Detection (BOD)
- Overvoltage Detection (OVD)
- Clock Supervisor (CSV)
- Hardware error correction (SECDED ECC) on all safety-critical memories (SRAM, flash, TCM)
• Low-power 2.7-V to 5.5-V operation
- Low-power Active, Sleep, Low-power Sleep, DeepSleep, and Hibernate modes for fine-grained power
management
- Configurable options for robust BOD
• Two threshold levels (2.7 V and 3.0 V) for BOD on VDDD and VDDA
• One threshold level (1.1 V) for BOD on VCCD
• Wakeup
- Up to two pins to wake from Hibernate mode
- Up to 220 GPIO pins to wake from Sleep modes
- Event Generator, SCB, Watchdog Timer, RTC alarms to wake from DeepSleep modes
• Clocks
- Internal Main Oscillator (IMO)
- Internal Low-Speed Oscillator (ILO)
- External Crystal Oscillator (ECO)
- Watch Crystal Oscillator (WCO)
- Phase-Locked Loop (PLL)
- Frequency-Locked Loop (FLL)
• Communication interfaces
- Up to eight CAN FD channels
• Increased data rate (up to 8 Mbps) compared to classic CAN, limited by physical layer topology and
transceivers
• Compliant with ISO 11898-1:2015
• Supports all the requirements of Bosch CAN FD Specification V1.0 for non-ISO CAN FD
• ISO 16845:2015 certificate available
- Up to 11 runtime-reconfigurable serial communication block (SCB) channels, each configurable as I2C, SPI,
or UART
- One 10/100 Mbps Ethernet MAC interface conforming to IEEE-802.3bw
• Supports the following PHY interfaces:
Media-independent interface (MII)
Reduced media-independent interface (RMII)
• Compliant with IEEE-802.1BA Audio Video Bridging (AVB)
• Compliant with IEEE-1588 Precision Time Protocol (PTP)
• External memory interface
- One SPI (Single, Dual, Quad, or Octal) or HYPERBUS™ interface
- On-the-fly encryption and decryption
- Execute-In-Place (XIP) from external memory
Datasheet
2
002-33896 Rev. *A
2022-10-20