XLH520024.000000I PDF预览

XLH520024.000000I

更新时间: 2025-09-18 19:42:35
品牌 Logo 应用领域
瑞萨 - RENESAS /
页数 文件大小 规格书
23页 536K
描述
频率(MHz):24 MHz;最小工作温度(℃):-40°C;最大工作温度(℃):85°C;安装类型:表面贴装型;封装:6-SMD,无引线;

XLH520024.000000I 数据手册

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XL Family of Low Phase Noise  
Quartz-based PLL Oscillators  
XL  
Datasheet  
Description  
Features  
Output types: LVDS, LVPECL, LVCMOS  
The Renesas XL devices (XO and VCXO options) are  
ultra-precision crystal oscillators with 750 to 890fs typical phase  
jitter over 12kHz to 20MHz bandwidth. Available in a wide  
frequency range from 0.750MHz to 1350MHz, the XL series  
crystal oscillators utilize a family of proprietary ASICs, with a key  
focus on noise reduction technologies.  
Phase jitter (12kHz to 20MHz): 750fs to 890fs typical  
Supply voltage: 2.5V or 3.3V  
Package options:  
3.2 × 2.5 × 1.0 mm (not available for VCXO)  
5.0 × 3.2 × 1.2 mm  
7.0 × 5.0 × 1.3 mm  
The 3rd order Delta Sigma Modulator reduces noise to the levels  
that are comparable to traditional Bulk Quartz and SAW  
oscillators. With short lead-time, low cost, low noise, wide  
frequency range, excellent ambient performance, the XL devices  
are an excellent choice over the conventional technologies. The  
XL (XO option) devices have stabilities as tight as ±20ppm and  
the XL (VCXO option) devices have ±50ppm APR. Either option  
provides extremely quick delivery for both standard and custom  
frequencies.  
Operating temperature: -20°C to +70°C  
Frequency stability options: ±20, ±25, ±50, or ±100 ppm  
(XO only)  
±50ppm APR (VCXO only)  
Operating temperature: -40°C to +85°C  
Frequency stability options: ±25, ±50, or ±100 ppm  
(XO only)  
±50ppm APR (VCXO only)  
Pin Assignments  
Operating temperature: -40°C to +105°C (XO only)  
Frequency stability options: ±50 or ±100 ppm  
kV of 85ppm/volt typical from 0.5VDC to VDD (VCXO only)  
Better than ±10% linearity for Vc range  
(XO Option)  
NOTE: To minimize power supply line noise, a 0.01μF bypass  
capacitor should be placed between VDD (Pin 6) and GND (Pin 3).  
6
1
5
4
2
3
(VCXO Option)  
NOTE: To minimize power supply line noise, a 0.01μF bypass  
capacitor should be placed between VDD (Pin 6) and GND (Pin 3).  
6
1
5
4
2
3
©2018-2022 Renesas Electronics Corporation  
1
March 2, 2022  
 
 
 
 
 

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