DM3730, DM3725
www.ti.com
SPRS685–AUGUST 2010
DM3730, DM3725
Applications Processor
Check for Samples: DM3730, DM3725
1 DM3730, DM3725 Applications Processor
1.1 Features
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Additional C64x+TM Enhancements
• DM3730/25 Applications Processor:
– Compatible with OMAP™ 3 Architecture
– MPU Subsystem
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–
Protected Mode Operation
Expectations Support for Error
Detection and Program Redirection
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•
Up to 1-GHz ARM CortexTM-A8 Core
NEON SIMD Coprocessor
–
Hardware Support for Modulo Loop
Operation
– High Performance Image, Video, Audio
– C64x+TM L1/L2 Memory Architecture
(IVA2.2TM) Accelerator Subsystem
Up to 800-MHz TMS320C64x+TM DSP Core
Enhanced Direct Memory Access (EDMA)
Controller (128 Independent Channels)
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32K-Byte L1P Program RAM/Cache
(Direct Mapped)
80K-Byte L1D Data RAM/Cache (2-Way
Set- Associative)
64K-Byte L2 Unified Mapped RAM/Cache
(4- Way Set-Associative)
32K-Byte L2 Shared SRAM and 16K-Byte
L2 ROM
•
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Video Hardware Accelerators
– POWERVR SGX™ Graphics Accelerator
(DM3730 only)
•
Tile Based Architecture Delivering up to
20 MPoly/sec
– C64x+TM Instruction Set Features
•
Universal Scalable Shader Engine:
Multi-threaded Engine Incorporating Pixel
and Vertex Shader Functionality
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Byte-Addressable (8-/16-/32-/64-Bit Data)
8-Bit Overflow Protection
Bit-Field Extract, Set, Clear
Normalization, Saturation, Bit-Counting
Compact 16-Bit Instructions
Additional Instructions to Support
Complex Multiplies
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Industry Standard API Support:
OpenGLES 1.1 and 2.0, OpenVG1.0
Fine Grained Task Switching, Load
Balancing, and Power Management
Programmable High Quality Image
Anti-Aliasing
– External Memory Interfaces:
– Advanced Very-Long-Instruction-Word
•
SDRAM Controller (SDRC)
(VLIW) TMS320C64x+TM DSP Core
–
16, 32-bit Memory Controller With
1G-Byte Total Address Space
•
•
Eight Highly Independent Functional
Units
Six ALUs (32-/40-Bit); Each Supports
Single 32- bit, Dual 16-bit, or Quad 8-bit,
Arithmetic per Clock Cycle
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–
Interfaces to Low-Power SDRAM
SDRAM Memory Scheduler (SMS) and
Rotation Engine
•
General Purpose Memory Controller
(GPMC)
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Two Multipliers Support Four 16 x 16-Bit
Multiplies (32-Bit Results) per Clock
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit
Results) per Clock Cycle
–
16-bit Wide Multiplexed Address/Data
Bus
–
Up to 8 Chip Select Pins With
128M-Byte Address Space per Chip
Select Pin
•
Load-Store Architecture With
Non-Aligned Support
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64 32-Bit General-Purpose Registers
Instruction Packing Reduces Code Size
All Instructions Conditional
–
Glueless Interface to NOR Flash,
NAND Flash (With ECC Hamming
Code Calculation), SRAM and
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Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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or design phase of development. Characteristic data and other
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