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XCV1600E-6FGG1156C

更新时间： 2024-01-27 14:26:38
品牌 Logo 应用领域
赛灵思 - XILINX 时钟栅可编程逻辑
页数 文件大小 规格书
10页 139K
描述
Field Programmable Gate Array, 7776 CLBs, 419904 Gates, 357MHz, 34992-Cell, CMOS, PBGA1156, FBGA-1156

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XCV1600E-6FGG1156C 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：BGA
包装说明：BGA, BGA1156,34X34,40针数：1156
Reach Compliance Code：compliantECCN代码：3A001.A.7.A
HTS代码：8542.39.00.01风险等级：5.81
最大时钟频率：357 MHzCLB-Max的组合延迟：0.47 ns
JESD-30 代码：S-PBGA-B1156JESD-609代码：e1
长度：35 mm湿度敏感等级：3
可配置逻辑块数量：7776等效关口数量：419904
输入次数：724逻辑单元数量：34992
输出次数：724端子数量：1156
最高工作温度：85 °C最低工作温度：
组织：7776 CLBS, 419904 GATES封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA1156,34X34,40
封装形状：SQUARE封装形式：GRID ARRAY
峰值回流温度（摄氏度）：245电源：1.2/3.6,1.8 V
可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY认证状态：Not Qualified
座面最大高度：2.6 mm子类别：Field Programmable Gate Arrays
最大供电电压：1.89 V最小供电电压：1.71 V
标称供电电压：1.8 V表面贴装：YES
技术：CMOS温度等级：OTHER
端子面层：TIN SILVER COPPER端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：40宽度：35 mm
Base Number Matches：1

XCV1600E-6FGG1156C 数据手册

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R
XCR3064XL 64 Macrocell CPLD  
0
14  
DS017 (v2.4) September 15, 2008  
Product Specification  
Features  
Description  
•
•
•
•
•
Low power 3.3V 64 macrocell CPLD  
5.5 ns pin-to-pin logic delays  
The CoolRunner™ XPLA3 XCR3064XL device is a 3.3V,  
64-macrocell CPLD targeted at power sensitive designs  
that require leading edge programmable logic solutions. A  
total of four function blocks provide 1,500 usable gates.  
Pin-to-pin propagation delays are as fast as 5.5 ns with a  
maximum system frequency of 192 MHz.  
System frequencies up to 192 MHz  
64 macrocells with 1,500 usable gates  
Available in small footprint packages  
-
-
-
-
44-pin VQFP (36 user I/O pins)  
48-ball CS BGA (40 user I/O pins)  
56-ball CP BGA (48 user I/O pins)  
100-pin VQFP (68 user I/O pins)  
TotalCMOS Design Technique for Fast  
Zero Power  
CoolRunner XPLA3 CPLDs offer a TotalCMOS solution,  
both in process technology and design technique. Xilinx  
employs a cascade of CMOS gates to implement its sum of  
products instead of the traditional sense amp approach.  
This CMOS gate implementation allows Xilinx to offer  
CPLDs that are both high performance and low power,  
breaking the paradigm that to have low power, you must  
have low performance. Refer to Figure 1 and Table 1 show-  
•
Optimized for 3.3V systems  
-
-
-
-
Ultra-low power operation  
Typical Standby Current of 17 μA at 25°C  
5V tolerant I/O pins with 3.3V core supply  
Advanced 0.35 micron five layer metal EEPROM  
process  
-
-
Fast Zero Power CMOS design technology  
3.3V PCI electrical specification compatible  
outputs (no internal clamp diode on any input or  
I/O, no minimum clock input capacitance)  
ing the I vs. Frequency of our XCR3064XL TotalCMOS  
CC  
CPLD (data taken with four resetable up/down, 16-bit  
counters at 3.3V, 25° C).  
•
Advanced system features  
45  
40  
35  
30  
25  
20  
15  
10  
5
-
-
-
-
-
-
-
-
In-system programming  
Input registers  
Predictable timing model  
Up to 23 available clocks per function block  
Excellent pin retention during design changes  
Full IEEE Standard 1149.1 boundary-scan (JTAG)  
Four global clocks  
Eight product term control terms per function block  
•
•
•
Fast ISP programming times  
Port Enable pin for dual function of JTAG ISP pins  
2.7V to 3.6V supply voltage at industrial temperature  
range  
Programmable slew rate control per macrocell  
Security bit prevents unauthorized access  
0
•
•
•
0
20 40 60 80 100 120 140 160 180  
Frequency (MHz)  
Refer to XPLA3 family data sheet (DS012) for  
DS017_01_062502  
architecture description  
Figure 1: I vs. Frequency at V = 3.3V, 25°C  
CC  
CC  
Table 1: I vs. Frequency (V = 3.3V, 25°C)  
CC  
CC  
Frequency  
(MHz)  
0
1
5
10  
20  
40  
60  
80  
100  
120  
140  
160  
180  
Typical I (mA) 0.017 0.24  
1.09  
2.15  
4.28  
8.50 12.85 16.80 20.80 25.72 29.89 33.53 36.27  
CC  
© 2000–2008 Xilinx, Inc. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS017 (v2.4) September 15, 2008  
Product Specification  
www.xilinx.com  
1
 
 
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