R
Platform Flash In-System Programmable Configuration PROMs
IEEE 1149.1 Boundary-Scan (JTAG)
The Platform Flash PROM family is compatible with the IEEE
1149.1 Boundary-Scan standard and the IEEE 1532 in-
system configuration standard. A Test Access Port (TAP) and
registers are provided to support all required Boundary-Scan
instructions, as well as many of the optional instructions
specified by IEEE Std. 1149.1. In addition, the JTAG interface
is used to implement in-system programming (ISP) to facilitate
configuration, erasure, and verification operations on the
Platform Flash PROM device. Table 5 lists the required and
optional Boundary-Scan instructions supported in the
Platform Flash PROMs. Refer to the IEEE Std. 1149.1
specification for a complete description of Boundary-Scan
architecture and the required and optional instructions.
Caution! The XCFxxP JTAG TAP pause states are not fully
compliant with the JTAG 1149.1 specification. If a temporary
pause of a JTAG shift operation is required, then stop the
JTAG TCK clock and maintain the JTAG TAP within the JTAG
Shift-IR or Shift-DR TAP state. Do not transition the XCFxxP
JTAG TAP through the JTAG Pause-IR or Pause-DR TAP state
to temporarily pause a JTAG shift operation.
Table 5: Platform Flash PROM Boundary-Scan Instructions
XCFxxS IR[7:0] XCFxxP IR[15:0]
Boundary-Scan Command
Instruction Description
(hex)
(hex)
Required Instructions
BYPASS
FF
01
00
FFFF
0001
0000
Enables BYPASS
SAMPLE/PRELOAD
EXTEST
Enables Boundary-Scan SAMPLE/PRELOAD operation
Enables Boundary-Scan EXTEST operation
Optional Instructions
CLAMP
FA
FC
FE
FD
00FA
00FC
00FE
00FD
Enables Boundary-Scan CLAMP operation
Places all outputs in high-impedance state simultaneously
Enables shifting out 32-bit IDCODE
HIGHZ
IDCODE
USERCODE
Enables shifting out 32-bit USERCODE
Platform Flash PROM Specific Instructions
Initiates FPGA configuration by pulsing CF pin Low once.
(For the XCFxxP this command also resets the selected
design revision based on either the external REV_SEL[1:0]
pins or on the internal design revision selection bits.)(1)
CONFIG
EE
00EE
Notes:
1. For more information see "Initiating FPGA Configuration," page 10.
XCFxxP Instruction Register (16 bits wide)
Instruction Register
The Instruction Register (IR) for the XCFxxP PROM is sixteen
bits wide and is connected between TDI and TDO during an
instruction scan sequence. The detailed composition of the
instruction capture pattern is illustrated in Table 7, page 6.
The Instruction Register (IR) for the Platform Flash PROM
is connected between TDI and TDO during an instruction
scan sequence. In preparation for an instruction scan
sequence, the instruction register is parallel loaded with a
fixed instruction capture pattern. This pattern is shifted out
onto TDO (LSB first), while an instruction is shifted into the
instruction register from TDI.
The instruction capture pattern shifted out of the XCFxxP
device includes IR[15:0]. IR[15:9] are reserved bits and are set
to a logic 0. The ISC Error field, IR[8:7], contains a 10 when an
ISC operation is a success; otherwise a 01 when an In-System
Configuration (ISC) operation fails. The Erase/Program
(ER/PROG) Error field, IR[6:5], contains a 10 when an erase
or program operation is a success; otherwise a 01 when an
erase or program operation fails. The Erase/Program
(ER/PROG) Status field, IR[4], contains a logic 0 when the
device is busy performing an erase or programming operation;
otherwise, it contains a logic 1. The ISC Status field, IR[3],
contains logic 1 if the device is currently in In-System
Configuration (ISC) mode; otherwise, it contains logic 0. The
DONE field, IR[2], contains logic 1 if the sampled design
revision has been successfully programmed; otherwise, a logic
0 indicates incomplete programming. The remaining bits
IR[1:0] are set to 01 as defined by IEEE Std. 1149.1.
XCFxxS Instruction Register (8 bits wide)
The Instruction Register (IR) for the XCFxxS PROM is eight
bits wide and is connected between TDI and TDO during an
instruction scan sequence. The detailed composition of the
instruction capture pattern is illustrated in Table 6, page 6.
The instruction capture pattern shifted out of the XCFxxS
device includes IR[7:0]. IR[7:5] are reserved bits and are set
to a logic 0. The ISC Status field, IR[4], contains logic 1 if
the device is currently in In-System Configuration (ISC)
mode; otherwise, it contains logic 0. The Security field,
IR[3], contains logic 1 if the device has been programmed
with the security option turned on; otherwise, it contains
logic 0. IR[2] is unused, and is set to '0'. The remaining bits
IR[1:0] are set to '01' as defined by IEEE Std. 1149.1.
DS123 (v2.17) October 26, 2009
www.xilinx.com
Product Specification
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