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XC7Z020-3CLG484C PDF预览

XC7Z020-3CLG484C

更新时间： 2024-09-25 20:56:35
品牌 Logo 应用领域
赛灵思 - XILINX /
页数 文件大小 规格书
52页 1974K
描述
Multifunction Peripheral,

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XC7Z020-3CLG484C 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：,Reach Compliance Code：compliant
风险等级：5.07JESD-609代码：e1
湿度敏感等级：3峰值回流温度（摄氏度）：260
端子面层：Tin/Silver/Copper (Sn96.5Ag3.0Cu0.5)处于峰值回流温度下的最长时间：30
Base Number Matches：1

XC7Z020-3CLG484C 数据手册

 浏览型号XC7Z020-3CLG484C的Datasheet PDF文件第2页浏览型号XC7Z020-3CLG484C的Datasheet PDF文件第3页浏览型号XC7Z020-3CLG484C的Datasheet PDF文件第4页浏览型号XC7Z020-3CLG484C的Datasheet PDF文件第5页浏览型号XC7Z020-3CLG484C的Datasheet PDF文件第6页浏览型号XC7Z020-3CLG484C的Datasheet PDF文件第7页 
Zynq-7000 All Programmable SoC  
(XC7Z010 and XC7Z020):  
DC and AC Switching Characteristics  
Preliminary Product Specification  
DS187 (v1.3) February 11, 2013  
Introduction  
The Zynq™-7000 All Programmable SoCs are available in  
-3, -2, and -1 speed grades, with -3 having the highest  
performance. Zynq-7000 device DC and AC characteristics  
are specified in commercial, extended, and industrial  
temperature ranges. Except the operating temperature  
range or unless otherwise noted, all the DC and AC  
electrical parameters are the same for a particular speed  
grade (that is, the timing characteristics of a -1 speed grade  
industrial device are the same as for a -1 speed grade  
commercial device). However, only selected speed grades  
and/or devices are available in the commercial, extended, or  
industrial temperature range.  
All supply voltage and junction temperature specifications  
are representative of worst-case conditions. The  
parameters included are common to popular designs and  
typical applications.  
This Zynq-7000 AP SoC (XC7Z010 and XC7Z020) data  
sheet, part of an overall set of documentation on the  
Zynq-7000 AP SoCs, is available on the Xilinx website at  
www.xilinx.com/zynq. All specifications are subject to  
change without notice.  
DC Characteristics  
Table 1: Absolute Maximum Ratings  
(1)  
Symbol  
Description  
Min  
Max  
Units  
Processing System (PS)  
VCCPINT  
VCCPAUX  
VCCPLL  
PS internal logic supply  
–0.5  
–0.5  
–0.5  
–0.5  
–0.5  
–0.5  
–0.5  
1.1  
V
V
V
V
V
V
V
PS auxiliary supply voltage  
PS PLL supply  
2.0  
2.0  
VCCO_DDR  
PS DDR I/O supply voltage  
PS MIO I/O supply voltage  
PS input reference voltage  
2.0  
(2)  
VCCO_MIO  
VPREF  
3.6  
2.0  
(2)(3)(4)(5)(6)  
VCCO_DDR + 0.5  
VPIN  
PS DDR and MIO I/O input voltage  
VCCO_MIO + 0.5  
–0.5  
2.625  
PS DDR and MIO I/O input voltage for VREF and differential I/O standards  
V
Programmable Logic (PL)  
1.1  
2.0  
VCCINT  
VCCAUX  
VCCBRAM  
VCCO  
PL internal supply voltage  
–0.5  
–0.5  
–0.5  
–0.5  
–0.5  
–0.5  
–0.5  
–0.5  
V
V
V
V
V
V
V
V
PL auxiliary supply voltage  
1.1  
PL supply voltage for the block RAM memories  
PL supply voltage for 3.3V HR I/O banks  
Input reference voltage  
3.6  
2.0  
VREF  
(3)(4)(5)(6)  
VCCO + 0.5  
2.625  
2.0  
VIN  
I/O input voltage  
I/O input voltage for VREF and differential I/O standards  
Key memory battery backup supply  
VCCBATT  
© Copyright 2011–2013 Xilinx, Inc. Xilinx, the Xilinx logo, Zynq, Virtex, Artix, Kintex, Spartan, ISE, Vivado and other designated brands included herein are trademarks of Xilinx  
in the United States and other countries. AMBA, AMBA Designer, ARM, Cortex-A9, CoreSight, Cortex, PrimeCell, ARM Powered, and ARM Connected Partner are trademarks  
of ARM Ltd. All other trademarks are the property of their respective owners.  
DS187 (v1.3) February 11, 2013  
www.xilinx.com  
Preliminary Product Specification  
1
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