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XC7Z010-1CLG225C PDF预览

XC7Z010-1CLG225C

更新时间： 2024-02-09 05:30:54
品牌 Logo 应用领域
赛灵思 - XILINX 时钟以太网：16GBASE-T
页数 文件大小 规格书
21页 610K
描述
Multifunction Peripheral, CMOS, PBGA225, BGA-225

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XC7Z010-1CLG225C 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：LFBGA,Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
Factory Lead Time：12 weeks风险等级：1.26
地址总线宽度：边界扫描：YES
总线兼容性：CAN; ETHERNET; I2C; SPI; UART; USB最大时钟频率：667 MHz
外部数据总线宽度：JESD-30 代码：S-PBGA-B225
JESD-609代码：e1长度：13 mm
湿度敏感等级：3I/O 线路数量：4
端子数量：225最高工作温度：85 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：LFBGA封装形状：SQUARE
封装形式：GRID ARRAY, LOW PROFILE, FINE PITCH峰值回流温度（摄氏度）：260
RAM（字数）：131072座面最大高度：1.5 mm
最大供电电压：1.05 V最小供电电压：0.95 V
标称供电电压：1 V表面贴装：YES
技术：CMOS温度等级：OTHER
端子面层：Tin/Silver/Copper (Sn96.5Ag3.0Cu0.5)端子形式：BALL
端子节距：0.8 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：30宽度：13 mm
Base Number Matches：1

XC7Z010-1CLG225C 数据手册

 浏览型号XC7Z010-1CLG225C的Datasheet PDF文件第2页浏览型号XC7Z010-1CLG225C的Datasheet PDF文件第3页浏览型号XC7Z010-1CLG225C的Datasheet PDF文件第4页浏览型号XC7Z010-1CLG225C的Datasheet PDF文件第5页浏览型号XC7Z010-1CLG225C的Datasheet PDF文件第6页浏览型号XC7Z010-1CLG225C的Datasheet PDF文件第7页 
Zynq-7000 All Programmable SoC Overview  
DS190 (v1.6) December 2, 2013  
Preliminary Product Specification  
Zynq-7000 All Programmable SoC First Generation Architecture  
The Zynq®-7000 family is based on the Xilinx All Programmable SoC architecture. These products integrate a feature-rich dual-core  
ARM® Cortex™-A9 based processing system (PS) and 28 nm Xilinx programmable logic (PL) in a single device. The ARM Cortex-A9  
CPUs are the heart of the PS and also include on-chip memory, external memory interfaces, and a rich set of peripheral connectivity  
interfaces.  
Processing System (PS)  
Dual-core ARM® Cortex™-A9 Based  
Application Processor Unit (APU)  
I/O Peripherals and Interfaces  
•
Two 10/100/1000 tri-speed Ethernet MAC peripherals with  
IEEE Std 802.3 and IEEE Std 1588 revision 2.0 support  
•
•
•
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2.5 DMIPS/MHz per CPU  
CPU frequency: Up to 1 GHz  
Coherent multiprocessor support  
ARMv7-A architecture  
•
•
•
Scatter-gather DMA capability  
Recognition of 1588 rev. 2 PTP frames  
GMII, RGMII, and SGMII interfaces  
•
Two USB 2.0 OTG peripherals, each supporting up to 12 Endpoints  
•
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TrustZone® security  
Thumb®-2 instruction set  
•
•
USB 2.0 compliant device IP core  
Supports on-the-go, high-speed, full-speed, and low-speed  
modes  
•
•
•
•
•
Jazelle® RCT execution Environment Architecture  
NEON™ media-processing engine  
Single and double precision Vector Floating Point Unit (VFPU)  
CoreSight™ and Program Trace Macrocell (PTM)  
Timer and Interrupts  
•
•
•
•
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Intel EHCI compliant USB host  
8-bit ULPI external PHY interface  
•
Two full CAN 2.0B compliant CAN bus interfaces  
•
CAN 2.0-A and CAN 2.0-B and ISO 118981-1 standard  
Three watchdog timers  
One global timer  
Two triple-timer counters  
compliant  
•
External PHY interface  
•
•
•
•
•
Two SD/SDIO 2.0/MMC3.31 compliant controllers  
Two full-duplex SPI ports with three peripheral chip selects  
Two high-speed UARTs (up to 1 Mb/s)  
Caches  
•
•
•
32 KB Level 1 4-way set-associative instruction and data caches  
(independent for each CPU)  
512 KB 8-way set-associative Level 2 cache  
(shared between the CPUs)  
Byte-parity support  
Two master and slave I2C interfaces  
GPIO with four 32-bit banks, of which up to 54 bits can be used with  
the PS I/O (one bank of 32b and one bank of 22b) and up to 64 bits  
(up to two banks of 32b) connected to the Programmable Logic  
Up to 54 flexible multiplexed I/O (MIO) for peripheral pin assignments  
•
On-Chip Memory  
Interconnect  
•
•
•
•
•
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On-chip boot ROM  
256 KB on-chip RAM (OCM)  
Byte-parity support  
High-bandwidth connectivity within PS and between PS and PL  
ARM AMBA® AXI based  
QoS support on critical masters for latency and bandwidth control  
External Memory Interfaces  
•
Multiprotocol dynamic memory controller  
Programmable Logic (PL)  
•
16-bit or 32-bit interfaces to DDR3, DDR3L, DDR2, or LPDDR2  
memories  
ECC support in 16-bit mode  
1GB of address space using single rank of 8-, 16-, or 32-bit-wide  
memories  
Static memory interfaces  
Configurable Logic Blocks (CLB)  
•
•
•
•
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Look-up tables (LUT)  
Flip-flops  
Cascadeable adders  
•
•
•
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8-bit SRAM data bus with up to 64 MB support  
Parallel NOR flash support  
ONFI1.0 NAND flash support (1-bit ECC)  
36 Kb Block RAM  
•
True Dual-Port  
•
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Up to 72 bits wide  
Configurable as dual 18 Kb  
•
1-bit SPI, 2-bit SPI, 4-bit SPI (quad-SPI), or two quad-SPI (8-bit)  
serial NOR flash  
DSP Blocks  
8-Channel DMA Controller  
•
•
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18 x 25 signed multiply  
48-bit adder/accumulator  
25-bit pre-adder  
•
Memory-to-memory, memory-to-peripheral, peripheral-to-memory,  
and scatter-gather transaction support  
© Copyright 2012–2013 Xilinx, Inc., Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx  
in the United States and other countries. AMBA, AMBA Designer, ARM, ARM Cortex-A9, CoreSight, Cortex, and PrimeCell are trademarks of ARM in the EU and other countries.  
PCI Express is a trademark of PCI-SIG and used under license. All other trademarks are the property of their respective owners.  
DS190 (v1.6) December 2, 2013  
www.xilinx.com  
Preliminary Product Specification  
1
 
 
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