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7 Series FPGAs Data Sheet: Overview
DS180 (v2.6.1) September 8, 2020
Product Specification
General Description
Xilinx® 7 series FPGAs comprise four FPGA families that address the complete range of system requirements, ranging from low cost, small form factor,
cost-sensitive, high-volume applications to ultra high-end connectivity bandwidth, logic capacity, and signal processing capability for the most demanding
high-performance applications. The 7 series FPGAs include:
•
•
Spartan®-7 Family: Optimized for low cost, lowest power, and high
I/O performance. Available in low-cost, very small form-factor
packaging for smallest PCB footprint.
•
Kintex®-7 Family: Optimized for best price-performance with a 2X
improvement compared to previous generation, enabling a new class
of FPGAs.
Artix®-7 Family: Optimized for low power applications requiring serial
transceivers and high DSP and logic throughput. Provides the lowest
total bill of materials cost for high-throughput, cost-sensitive
applications.
•
Virtex®-7 Family: Optimized for highest system performance and
capacity with a 2X improvement in system performance. Highest
capability devices enabled by stacked silicon interconnect (SSI)
technology.
Built on a state-of-the-art, high-performance, low-power (HPL), 28 nm, high-k metal gate (HKMG) process technology, 7 series FPGAs enable an
unparalleled increase in system performance with 2.9 Tb/s of I/O bandwidth, 2 million logic cell capacity, and 5.3 TMAC/s DSP, while consuming 50% less
power than previous generation devices to offer a fully programmable alternative to ASSPs and ASICs.
Summary of 7 Series FPGA Features
•
•
•
•
Advanced high-performance FPGA logic based on real 6-input look-
up table (LUT) technology configurable as distributed memory.
•
Powerful clock management tiles (CMT), combining phase-locked
loop (PLL) and mixed-mode clock manager (MMCM) blocks for high
precision and low jitter.
Quickly deploy embedded processing with MicroBlaze™ processor.
Integrated block for PCI Express® (PCIe), for up to x8 Gen3
Endpoint and Root Port designs.
Wide variety of configuration options, including support for
commodity memories, 256-bit AES encryption with HMAC/SHA-256
authentication, and built-in SEU detection and correction.
Low-cost, wire-bond, bare-die flip-chip, and high signal integrity flip-
chip packaging offering easy migration between family members in
the same package. All packages available in Pb-free and selected
packages in Pb option.
Designed for high performance and lowest power with 28 nm,
HKMG, HPL process, 1.0V core voltage process technology and
0.9V core voltage option for even lower power.
36 Kb dual-port block RAM with built-in FIFO logic for on-chip data
buffering.
High-performance SelectIO™ technology with support for DDR3
interfaces up to 1,866 Mb/s.
High-speed serial connectivity with built-in multi-gigabit transceivers
from 600 Mb/s to max. rates of 6.6 Gb/s up to 28.05 Gb/s, offering a
special low-power mode, optimized for chip-to-chip interfaces.
•
•
•
•
•
•
A user configurable analog interface (XADC), incorporating dual
12-bit 1MSPS analog-to-digital converters with on-chip thermal and
supply sensors.
DSP slices with 25 x 18 multiplier, 48-bit accumulator, and pre-adder
for high-performance filtering, including optimized symmetric
coefficient filtering.
•
Table 1: 7 Series Families Comparison
Max. Capability
Logic Cells
Spartan-7
Artix-7
215K
Kintex-7
478K
Virtex-7
1,955K
102K
Block RAM(1)
4.2 Mb
13 Mb
34 Mb
68 Mb
DSP Slices
160
740
1,920
3,600
DSP Performance(2)
MicroBlaze CPU(3)
Transceivers
176 GMAC/s
929 GMAC/s
303 DMIPs
16
2,845 GMAC/s
438 DMIPs
32
5,335 GMAC/s
441 DMIPs
96
260 DMIPs
–
Transceiver Speed
Serial Bandwidth
PCIe Interface
Memory Interface
I/O Pins
–
6.6 Gb/s
211 Gb/s
x4 Gen2
1,066 Mb/s
500
12.5 Gb/s
800 Gb/s
x8 Gen2
1,866 Mb/s
500
28.05 Gb/s
2,784 Gb/s
x8 Gen3
1,866 Mb/s
1,200
–
–
800 Mb/s
400
I/O Voltage
1.2V–3.3V
1.2V–3.3V
1.2V–3.3V
1.2V–3.3V
Low-Cost, Wire-Bond,
Bare-Die Flip-Chip
Bare-Die Flip-Chip and High-
Performance Flip-Chip
Highest Performance
Flip-Chip
Package Options
Low-Cost, Wire-Bond
Notes:
1.
2.
3.
Additional memory available in the form of distributed RAM.
Peak DSP performance numbers are based on symmetrical filter implementation.
Peak MicroBlaze CPU performance numbers based on microcontroller preset.
© Copyright 2010–2020 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, Kintex, Spartan, UltraScale, Versal, Virtex, Vivado, Zynq, and other designated brands included herein
are trademarks of Xilinx in the United States and other countries. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property of their
respective owners.
DS180 (v2.6.1) September 8, 2020
www.xilinx.com
Product Specification
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