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XC6115A521EL PDF预览

XC6115A521EL

更新时间: 2024-02-27 08:13:31
品牌 Logo 应用领域
特瑞仕 - TOREX 光电二极管
页数 文件大小 规格书
27页 411K
描述
Power Supply Management Circuit, Fixed, 1 Channel, CMOS, PDSO6, USP-6

XC6115A521EL 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:HTSON,Reach Compliance Code:compliant
风险等级:5.72其他特性:DETECT VOLTAGE IS 2.1 V
可调阈值:NO模拟集成电路 - 其他类型:POWER SUPPLY MANAGEMENT CIRCUIT
JESD-30 代码:R-PDSO-N6长度:2 mm
湿度敏感等级:1信道数量:1
功能数量:1端子数量:6
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:HTSON
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, HEAT SINK/SLUG, THIN PROFILE
峰值回流温度(摄氏度):260座面最大高度:0.6 mm
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):1 V
标称供电电压 (Vsup):2 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:NO LEAD端子位置:DUAL
处于峰值回流温度下的最长时间:10宽度:1.8 mm
Base Number Matches:1

XC6115A521EL 数据手册

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XC6101 ~ XC6107, XC6111~ XC6117  
Series  
OPERATIONAL EXPLANATION  
The XC6101~XC6107, XC6111~XC6117 series compare, using the amplifier, the voltage of the internal voltage reference  
source with the voltage divided by R1, R2 and R3 connected to the VIN pin. The resulting output signal from the error  
amplifier activates the watchdog logic, manual reset logic, delay circuit and the output driver. When the VIN pin voltage  
gradually falls and finally reaches the detect voltage, the RESETB pin output goes from high to low in the case of the VDFL type  
ICs, and the RESET pin output goes from low to high in the case of the VDFH type ICs.  
<RESETB / RESET Pin Output Signal>  
* VDFL (RESETB) type - output signal: Low when detected.  
The RESETB pin output goes from high to low whenever the VIN pin voltage falls below the detect voltage, or whenever the  
MRB pin is driven from high to low. The RESETB pin remains low for the release delay time (TDR) after the VIN pin voltage  
reaches the release voltage. If neither rising nor falling signals are applied to the WD pin within the watchdog timeout period,  
the RESETB pin output remains low for the release delay time (TDR), and thereafter the RESET pin outputs high level signal.  
* VDFH (RESET) type – output signal: High when detected.  
The RESET pin output goes from low to high whenever the VIN pin voltage falls below the detect voltage, or whenever the  
MRB pin is driven from high to low. The RESET pin remains high for the release delay time (TDR) after the VIN pin voltage  
reaches the release voltage. If neither rising nor falling signals are applied to the WD pin within the watchdog timeout period,  
the VOUT pin output remains high for the release delay time (TDR), and thereafter the RESET pin outputs low level signal.  
<Hysteresis>  
When the internal comparator output is high, the N-Channel transistor connected in parallel to R3 is turned ON, activating the  
hysteresis circuit. The difference between the release and detect voltages represents the hysteresis width, as shown by the  
following calculations:  
VDF (detect voltage) = (R1+R2+R3) x Vref(R2+R3)  
VDR (release voltage) = (R1+R2) x Vref(R2)  
VHYS (hysteresis width)=VDR-VDF (V)  
VDR > VDF  
* Detect voltage (VDF) includes conditions of both VDFL (low when detected) and VDFH (high when detected).  
* Please refer to the block diagrams for R1, R2, R3 and Vref.  
Hysteresis width is selectable from VDF x 0.05V (XC6101~XC6107) or VDF x 0.001V (XC6111~XC6117).  
<Watchdog (WD) Pin>  
The XC6101~XC6107, XC6111~XC6117 series use a watchdog timer to detect malfunction or “runaway” of the  
microprocessor. If neither rising nor falling signals are applied from the microprocessor within the watchdog timeout period,  
the RESETB/RESET pin output maintains the detection state for the release delay time (TDR), and thereafter the  
RESET/RESETB pin output returns to the release state (Please refer to the FUNCTION CHART). The timer in the watchdog  
is then restarted. Six watchdog timeout period settings are available in 1.6s, 400ms, 200ms, 100ms, 50ms, 6.25ms.  
<MRB Pin>  
Using the MRB voltage pin input, the RESET/RESETB pin signal can be forced to the detection state. When the MRB pin is  
driven from high to low, the RESETB pin output goes from high to low level signal in the case of the VDFL type ICs, and the  
RESET pin output goes from low to high in the case of the VDFH type. Even after the MRB pin is driven back high, the  
RESET/RESETB pin output maintains the detection state for the release delay time (TDR). Since the MRB pin is internally  
pulled up to the VIN pin voltage level, leave the MRB pin open if unused (Please refer to the FUNCTION CHART). A diode,  
which is an input protection element, is connected between the MRB pin and VIN pin. Therefore, if the MRB pin is applied  
voltage that exceeds VIN, the current will flow to VIN through the diode. Please use this IC within the stated maximum ratings  
(VSS-0.3VIN+0.37.0V) on the MRB pin.  
<Release Delay Time>  
Release delay time (TDR) is the time that elapses from when the VIN pin reaches the release voltage, or when the watchdog  
timeout period expires with no rising signal applied to the WD pin, until the RESET/RESETB pin output is released from the  
detection state. Seven release delay time (TDR) watchdog timeout period settings are available in 1.6s, 400ms, 200ms,  
100ms, 50ms, 25ms, 3.13ms.  
<Detect Delay Time>  
Detect Delay Time (TDF) is the time that elapses from when the VIN pin voltage falls to the detect voltage until the RESET/  
RESETB pin output goes into the detection state.  
9/27  

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