Datasheet > XC5VFX100T-1FFG1136C

XC5VFX100T-1FFG1136C

更新时间： 2023-08-15 00:00:00

品牌	Logo	应用领域
赛灵思 - XILINX		栅
页数	文件大小	规格书
15页	328K
描述
Field Programmable Gate Array, 8960 CLBs, 1098MHz, 102400-Cell, CMOS, PBGA1136, 35 X 35 MM, LEAD FREE, FBGA-1136

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Virtex-5 Family Overview

Virtex-5 LXT, SXT, TXT, and FXT Platform Features

This section briefly describes blocks available only in LXT, SXT, TXT, and FXT devices.

Tri-Mode (10/100/1000 Mb/s) Ethernet MACs

Integrated Endpoint Blocks for PCI Express

Virtex-5 LXT, SXT, TXT, and FXT devices contain up to eight

embedded Ethernet MACs, two per Ethernet MAC block.

The blocks have the following characteristics:

Virtex-5 LXT, SXT, TXT, and FXT devices contain up to four

integrated Endpoint blocks. These blocks implement

Transaction Layer, Data Link Layer, and Physical Layer

functions to provide complete PCI Express Endpoint

functionality with minimal FPGA logic utilization. The blocks

have the following characteristics:

•

Designed to the IEEE 802.3-2002 specification

UNH-compliance tested

RGMII/GMII Interface with SelectIO or SGMII interface

when used with RocketIO transceivers

Half or full duplex

•

Compliant with the PCI Express Base Specification 1.1

Works in conjunction with RocketIO transceivers to

provide complete endpoint functionality

•

Supports Jumbo frames

1000 Base-X PCS/PMA: When used with RocketIO

GTP transceiver, can provide complete 1000 Base-X

implementation on-chip

•

1, 4, or 8 lane support per block

•

DCR-bus connection to microprocessors

Virtex-5 LXT and SXT Platform Features

This section briefly describes blocks available only in LXT and SXT devices.

RocketIO GTP Transceivers

4 - 24 channel RocketIO GTP transceivers capable of

running 100 Mb/s to 3.75 Gb/s.

•

Programmable transmitter output swing

Programmable receiver equalization

Programmable receiver termination

Embedded support for:

•

Full clock and data recovery

8/16-bit or 10/20-bit datapath support

Optional 8B/10B or FPGA-based encode/decode

Integrated FIFO/elastic buffer

Channel bonding and clock correction support

Embedded 32-bit CRC generation/checking

Integrated comma-detect or A1/A2 detection

Programmable pre-emphasis (AKA transmitter

equalization)

−

Out of Band (OOB) signalling: Serial ATA

Beaconing, electrical idle, and PCI Express receiver

detection

•

Built-in PRBS generator/checker

Virtex-5 FPGA RocketIO GTP transceivers are further

discussed in the Virtex-5 FPGA RocketIO GTP Transceiver

User Guide.

DS100 (v5.1) August 21, 2015

www.xilinx.com

Product Specification

1...6 7 8910 11 12...15

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XC5VFX100T-2FFG1738C	XILINX	Field Programmable Gate Array, 8960 CLBs, 1265MHz, 102400-Cell, CMOS, PBGA1738, 42.50 X 42	获取价格
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