CPU_RST_V1P1_N
56
OUT
CPU, CLOCKS + EEPROM + STRAPPING
CPU_CLK_DP
R7R4
1
2
CPU_RST_N
34
IN
IN
3.92K
402
1%
CH
1
46
46
IN
IN
C7R112
360PF
10%
R7R16
N: STUFF C?,C? WITH ZERO OHM R'S FOR WN
N: STUFF C?,C? WITH .01UF CAPS FOR SHIVA
1
2
1
FT2P11
FT2P12
FTP
6.19K
402
1%
CH
50V
1
2
NPO
FTP
603
R7R10
1
2
CPU_PWRGD
CPU_PWRGD_V1P1_N
34
CPU_CLK_DN
3.92K
402
1%
CH
1
R7R11
1
2
V_GPUCORE
V_GPUCORE
C7R113
360PF
10%
U7D1
1
OF 10
IC
6.19K
402
1%
CH
V_GPUCORE
50V
TP7R1
PROBE
2
CPU VERSION
20
NPO
R6R4
2
1
1
603
CPU_CORE_IF_BGR_PLL
VREG_EFUSE_EN
OUT
AJ25
AH25
AK17
C6
1
CORE_CLK_DP
CORE_CLK_DN
CORE_IF_BGR_PLL
2
1
1
1K
402
5%
CH
TP6D1
2
1
PROBE
SMT
R6D1
931
R6D2
1.07K
1%
CH
402
1
1
SMT
R6R6
10K
5%
AJ2
AF16
HARD_RESET_B
POWER_GOOD
EFU_POWERON
55
R6R9
10K
2
1%
R6R5
2
CH
402
5%
1K
402
5%
CH
EMPTY
FSB_CLK_DP
FSB_CLK_DN
CPU_FSB_HF_CLKOUT_DP
CPU_FSB_HF_CLKOUT_DN
AK23
AK22
AH22
AJ22
CH
402
FSB_CLK_DP
FSB_CLK_DN
FSB_HF_CLKOUT_DP
FSB_HF_CLKOUT_DN
2
OUT
OUT
402
2
2
1
CPU_FSB_CLK_SEL
CPU_EXT_CLK_EN
CPU_PLL_BYPASS
CPU_FSB_IMPED_CAL_DP
CPU_FSB_IMPED_CAL_DN
AG18
AF18
AH16
AJ16
AG16
AK25
AK24
FSB_CLK_SEL
EXT_CLK_EN
PLL_BYPASS
FSB_IMPED_CAL_DP
FSB_IMPED_CAL_DN
TP7R3
PROBE
R6R8
10K
5%
EMPTY
402
CPU_RES0_DP
CPU_RES0_DN
1
AK14
AK15
1
2
RESISTOR0_DP
RESISTOR0_DN
1
R6R7
10K
CPU_PULSE_LIMIT_BYPASS
PULSE_LIMIT_BYPASS
TRIGGER_IN
TP7R4
PROBE
R7R17
10K
SMT
1
5%
R7R24
1
2
CPU_TRIGGER_IN
2
CPU_VDDS0_DP
CPU_VDDS0_DN
AH13
AK12
1
2
5%
CH
402
2
VDDS0_DP
VDDS0_DN
R7D1
10K
10K
402
5%
CH
CH
402
TP7R2
PROBE
5%
V_GPUCORE
2
SMT
CPU_SYS_CONFIG0
CPU_SYS_CONFIG1
CPU_VDDS1_DP
CPU_VDDS1_DN
AK3
AH1
AJ4
AK5
1
2
CH
402
SYS_CONFIG0
SYS_CONFIG1
VDDS1_DP
VDDS1_DN
2
SMT
CPU_POST_IN<0..4>
DB7R1
TP
AH10
AJ10
AK9
AK10
AK11
0
1
POST_IN0
POST_IN1
POST_IN2
POST_IN3
POST_IN4
OUT
CPU_PSRO0_OUT
1
1
AK16
1
PSRO0_OUT
2
3
4
TP6R1
R7R15
10K
5%
R7R8
10K
5%
1
PROBE
CPU_ANL_1
1
2
R7R9
10K
EMPTY
402
EMPTY
402
SMT
5%
CH
402
CPU_SPI_SI
CPU_SPI_CLK
CPU_SPI_EN
CPU_SPI_SO
B3
A2
B2
A3
2
1
2
1
4
SPI_SI
SPI_CLK
SPI_EN
SPI_SO
4
IN
OUT
4
OUT
OUT
LAYOUT: MUST BE ACCESSIBLE
1
2
R6R10
2
1
4
2
CPU_ANL_1_R
C6R46
10UF
10%
R6E1
10K
5.11K
402
1%
EMPTY
CPU_TEMP_P
CPU_TEMP_N
AK20
AK21
TEMP_P
TEMP_N
29
29
R7R6
10K
5%
CH
402
IN
OUT
6.3V
AG24
AF24
5%
2
ANL_1
ANL_2
EMPTY
1206
R7R7
10K
5%
CH
402
CPU_ANL_2
CH
402
CPU_VREG_APS0
CPU_VREG_APS1
CPU_VREG_APS2
CPU_VREG_APS3
CPU_VREG_APS4
CPU_VREG_APS5
C4
B5
A4
B4
A5
C5
VID0
VID1
VID2
VID3
VID4
VID5
49
1
OUT
OUT
OUT
OUT
OUT
OUT
CPU_SPARE0
CPU_SPARE1
AK1
AJ1
SPARE0
SPARE1
49
2
TP6R2
49
49
49
49
2
PROBE
1
2
CPU_TEST_EN
AH4
TE
V_GPUCORE
SMT
1
1
1
1
1
FTP FT7T5
FTP FT7T4
FTP FT7T3
FTP FT7T2
FTP FT7T1
FTP FT7T7
X02046-002
R7R14
10K
5%
CH
402
2
1
J7F1
2X3HDR
1
1
1
1
1
1
1
1
CPU_SPI_SI
CPU_SPI_WP_N
1
3
5
2
4
6
4
R7R1
R7R2
OUT
OUT
R7R21
10K
5%
R7R12
10K
5%
R7R13
10K
5%
R7R22
10K
5%
R7R23
10K
5%
4
0
0
V_MEM
V_MEM
5%
5%
EMPTY
402
EMPTY
402
CH
CH
CH
CH
CH
EMPTY
402
402
402
402
402
2
2
1
1
2
1
2
1
2
1
2
1
2
1
C6F1
.1UF
10%
6.3V
X5R
402
V_MEM
R7F3
0
1
2
3
4
10K
5%
U7E1
IC
2
AT25020A
EMPTY
402
R6E2
CPU_SPI_CLK
CPU_SPI_CLK_R
CPU_SPI_SO_R
6
5
8
2
4
4
SCK
SDI
VCC
IN
IN
2
R7R20
10K
5%
EMPTY
402
R7R5
10K
5%
EMPTY
402
R7R3
10K
5%
EMPTY
402
R7R19
10K
5%
EMPTY
402
R7R18
10K
5%
EMPTY
402
1K
5%
CH
R7F7
2
1
CPU_SPI_SI_R
CPU_SPI_SI
402
SDO
GND
4
OUT
7
1
3
HOLD_N*
CS_N*
WP_N*
1K
5%
CH
R7E7
CPU_SPI_SO
V_MEM
CPU_SPI_EN_R
402
1
4
2
2
2
2
2
1K
402
5%
CH
1
1
1
1
1
R7F4
100
5%
4
3
V_MEM
FT7R4 FTP
FT7R6 FTP
FT7R2 FTP
FT7R1 FTP
FT7R5 FTP
X800552-001
2
1
0
R7E8
2
1
1
CH
402
1
2
10K
402
5%
CH
R7U3
10K
5%
R7F1
CH
402
2
2
10K
402
5%
R7F2
CPU_SPI_EN
CPU_SPI_WP_N
EMPTY
4
4
IN
IN
1K
402
5%
CH
DRAWING
XENON_FABK
Wed Aug 03 14:50:50
PROJECT NAME
XENON_RETAIL
PAGE
4/73
REV
MICROSOFT
[PAGE_TITLE=CPU,
CLOCKS + EEPROM + STRAPPING]
2005
K6
CONFIDENTIAL
5秒后页面跳转
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