Datasheet > XA6SLX45T-3FGG484Q

XA6SLX45T-3FGG484Q

更新时间： 2024-01-17 10:29:40

品牌	Logo	应用领域
赛灵思 - XILINX		时钟栅可编程逻辑
页数	文件大小	规格书
10页	288K
描述
Field Programmable Gate Array, 62.5MHz, 43661-Cell, PBGA484,

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XA6SLX45T-3FGG484Q 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	BGA, BGA484,22X22,40	Reach Compliance Code：	compliant
ECCN代码：	3A991.D	HTS代码：	8542.39.00.01
Factory Lead Time：	12 weeks	风险等级：	2.07
最大时钟频率：	62.5 MHz	JESD-30 代码：	S-PBGA-B484
JESD-609代码：	e1	湿度敏感等级：	3
输入次数：	296	逻辑单元数量：	43661
输出次数：	296	端子数量：	484
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装等效代码：	BGA484,22X22,40	封装形状：	SQUARE
封装形式：	GRID ARRAY	峰值回流温度（摄氏度）：	250
电源：	1.2,2.5/3.3 V	可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY
认证状态：	Not Qualified	筛选级别：	AEC-Q100
子类别：	Field Programmable Gate Arrays	表面贴装：	YES
端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	30	Base Number Matches：	1

XA6SLX45T-3FGG484Q 数据手册

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XA Spartan-6 Automotive FPGA Family Overview

Clock Distribution

Each XA Spartan-6 FPGA provides abundant clock lines to address the different clocking requirements of high fanout, short

propagation delay, and extremely low skew.

Global Clock Lines

In each XA Spartan-6 FPGA, 16 global-clock lines have the highest fanout and can reach every flip-flop clock. Global clock

lines must be driven by global clock buffers, which can also perform glitchless clock multiplexing and the clock enable

function. Global clocks are often driven from the CMTs, which can completely eliminate the basic clock distribution delay.

I/O Clocks

I/O clocks are especially fast and serve only the localized input and output delay circuits and the I/O serializer/deserializer

(SERDES) circuits, as described in the I/O Logic section.

Block RAM

Every XA Spartan-6 FPGA has between 12 and 268 dual-port block RAMs, each storing 18 Kb. Each block RAM has two

completely independent ports that share only the stored data.

Synchronous Operation

Each memory access, whether read or write, is controlled by the clock. All inputs, data, address, clock enables, and write

enables are registered. The data output is always latched, retaining data until the next operation. An optional output data

pipeline register allows higher clock rates at the cost of an extra cycle of latency.

During a write operation in dual-port mode, the data output can reflect either the previously stored data, the newly written

data, or remain unchanged.

Programmable Data Width

•

Each port can be configured as 16K × 1, 8K × 2, 4K × 4, 2K × 9 (or 8), 1K × 18 (or 16), or 512 x 36 (or 32).

The x9, x18, and x36 configurations include parity bits. The two ports can have different aspect ratios.

Each block RAM can be divided into two completely independent 9 Kb block RAMs that can each be configured to any

aspect ratio from 8K x 1 to 512 x 18, with 256 x 36 supported in simple dual-port mode.

Memory Controller Block

Most XA Spartan-6 devices include dedicated memory controller blocks (MCBs), each targeting a single-chip DRAM (either

DDR, DDR2, DDR3, or LPDDR), and supporting access rates of up to 800 Mb/s.

The MCB has dedicated routing to predefined FPGA I/Os. If the MCB is not used, these I/Os are available as general

purpose FPGA I/Os. The memory controller offers a complete multi-port arbitrated interface to the logic inside the XA

Spartan-6 FPGA. Commands can be pushed, and data can be pushed to and pulled from independent built-in FIFOs, using

conventional FIFO control signals. The multi-port memory controller can be configured in many ways. An internal 32-, 64-,

or 128-bit data interface provides a simple and reliable interface to the MCB.

The MCB can be connected to 4-, 8-, or 16-bit external DRAM. The MCB, in many applications, provides a faster DRAM

interface compared to traditional internal data buses, which are wider and are clocked at a lower frequency. The FPGA logic

interface can be flexibly configured irrespective of the physical memory device.

Digital Signal Processing—DSP48A1 Slice

DSP applications use many binary multipliers and accumulators, best implemented in dedicated DSP slices. All XA

Spartan-6 FPGAs have many dedicated, full-custom, low-power DSP slices, combining high speed with small size, while

retaining system design flexibility.

Each DSP48A1 slice consists of a dedicated 18 × 18 bit two’s complement multiplier and a 48-bit accumulator, both capable

of operating at up to 390 MHz. The DSP48A1 slice provides extensive pipelining and extension capabilities that enhance

DS170 (v1.3) December 13, 2012

www.xilinx.com

Product Specification

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XA6SLX75-2FGG484I	XILINX	Field Programmable Gate Array, 62.5MHz, 74637-Cell, PBGA484,	获取价格
XA6SLX75-2FGG484Q	XILINX	Field Programmable Gate Array, 62.5MHz, 74637-Cell, PBGA484,	获取价格
XA6SLX75-3FGG484Q	XILINX	Field Programmable Gate Array, 62.5MHz, 74637-Cell, PBGA484,	获取价格
XA6SLX75T-2FGG484I	XILINX	Field Programmable Gate Array, 62.5MHz, 74637-Cell, PBGA484,	获取价格

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