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X9251TV24IZT1 PDF预览

X9251TV24IZT1

更新时间： 2024-11-19 15:58:11
品牌 Logo 应用领域
瑞萨 - RENESAS 光电二极管
页数 文件大小 规格书
20页 331K
描述
QUAD 100K DIGITAL POTENTIOMETER, INCREMENT/DECREMENT CONTROL INTERFACE, 256 POSITIONS, PDSO24, 4.40 MM, ROHS COMPLIANT, TSSOP-24

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X9251TV24IZT1 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP, TSSOP24,.25针数：24
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.58
Base Number Matches：1

X9251TV24IZT1 数据手册

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X9251  
®
Single Supply/Low Power/256-Tap/SPI Bus  
Data Sheet  
April 13, 2007  
FN8166.5  
Quad Digitally-Controlled (XDCP™)  
Potentiometer  
Features  
• Four potentiometers in one package  
The X9251 integrates four digitally controlled potentio-  
meters (XDCP) on a monolithic CMOS integrated circuit.  
• 256 resistor taps–0.4% resolution  
• SPI Serial Interface for write, read, and transfer operations  
of the potentiometer  
The digitally controlled potentiometers are imple-mented  
with a combination of resistor elements and CMOS switches.  
The position of the wipers are controlled by the user through  
the SPI bus interface. Each potentiometer has associated  
with it a volatile Wiper Counter Register (WCR) and four  
non-volatile Data Registers that can be directly written to and  
read by the user. The content of the WCR controls the  
position of the wiper. At power-up, the device recalls the  
content of the default Data Registers of each DCP (DR00,  
DR10, DR20, and DR30) to the corresponding WCR.  
• Wiper resistance: 100Ω typical @ V  
CC  
= 5V  
• 4 Non-volatile data registers for each  
potentiometer  
• Non-volatile storage of multiple wiper positions  
• Standby current <5µA max  
• V : 2.7V to 5.5V Operation  
CC  
• 50kΩ, 100kΩ versions of total resistance  
• 100 year data retention  
The XDCP can be used as a three-terminal potentiometer or  
as a two terminal variable resistor in a wide variety of  
applications including control, parameter adjustments, and  
signal processing.  
• Single supply version of X9250  
• Endurance: 100,000 data changes per bit per register  
• 24 Ld SOIC, 24 Ld TSSOP  
• Low power CMOS  
• Pb-free plus anneal available (RoHS compliant)  
Functional Diagram  
R
R
H3  
R
R
H2  
V
H1  
H0  
CC  
HOLD  
DCP1  
DCP3  
DCP2  
DCP0  
WCR1  
DR10  
DR11  
DR12  
DR13  
WCR3  
DR30  
DR31  
DR32  
DR33  
WCR2  
DR20  
DR21  
DR22  
DR23  
WCR0  
DR00  
DR01  
DR02  
DR03  
A1  
A0  
SO  
SI  
SPI  
Interface  
POWER UP,  
INTERFACE  
CONTROL  
AND  
STATUS  
SCK  
CS  
V
R
R
L3  
R
SS  
R
R
R
W3  
R
WP  
R
W0  
L1  
L2  
L0  
W1  
W2  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2007. All Rights Reserved  
All other trademarks mentioned are the property of their respective owners.  
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