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X5114

更新时间： 2024-10-03 03:15:15

品牌	Logo	应用领域
XICOR		控制器
页数	文件大小	规格书
40页	562K
描述
System Controller

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中文翻译

获取价格

数据手册

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X5114 数据手册

X5114

System Controller

FEATURES

DESCRIPTION

• Simpliﬁes Backplane Communications

• Monitor Fault and “Hot Docking” Conditions

• Ten Level Selectable Input Threshold

• Two Fully Redundant SPI Serial I/O Ports

• Programmable Output or Input Port Pins

—16 General I/O pins

The X5114 is a single-chip system controller that is used

in applications such as multiprocessing, telecommunica-

tions, data communications, cable systems, set top

boxes, etc. The chip can implement features such as

backplane communication, hot docking, cable diagnos-

tics, etc.

—8 bit Port with 4 Handshake Modes

• Single Read Input Mode

The X5114 makes extensive use of nonvolatile memory

with 4,096 bits of general purpose EEPROM, nonvolatile

conﬁguration registers, and nonvolatile programming of

the port pins. The ports can be set up as sixteen general

I/Os with pin selectable data direction (including eight

inputs with nonvolatile threshold selections) or as an

eight bit port with handshake. The chip is controlled via

two redundant 2MHz SPI serial ports.

• Multiple Read Input Mode

• Output Mode

• Bidirectional Mode

—Port Tristate Control

• Programmable Interrupt and Mask Options

• 8-bit Direct Address Decoder allows Cascaded

255+ devices on one SPI bus

• 4K bits of EEPROM with 32 byte page write

• Default Output Data on Port at Power-up

• High Reliability EEPROM

A sophisticated interrupt controller provides notiﬁcation of

a failed SPI command, changing conditions on an input,

handshake status, and I/O errors. Interrupts are

maskable.

—Endurance - 10⁵Data Changes

—Data Retention - 100 years

On-chip EEPROM provides nonvolatile storage of

system status, manufacturing information, board ID or

other parameters.

• 44-Pin PLCC, 48-Lead TQFP

FUNCTIONAL DIAGRAM

Port A Each Pin

PA7

CSO

CSC

PA6

PA5

PA4

PA3

PA2

PA1

PA0

Desired

Value

Output

Input

CSa

Port A

Latch

SIa

SPI_A

SOa

Interrupt

Logic

Threshold

Adjust

SCKa

Serial

Engine/

Data Flow

Controller

CSb

SIb

IRQA

IRQB

PCE

SPI_B

Interrupt

Control A/B

SOb

SCKb

Port

Config

Regs

Handshake

Logic

(PB7-PB4)

Interrupt

Logic

Address

Select

Decode

256 X 8

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

Desired

Value

Output

256 X 8

Port A

Handshake

Port B

Latch

EEPROM

Input

= EEPROM

Port B Each Pin

Xicor, Inc. 1994 - 1997 Patents Pending

7054-1.2 10/29/00 T13/C8/D24 SH

Characteristics subject to change without notice

12 3 4 5 6 7...40

中文翻译

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