X46402V8E-2.9

更新时间： 2024-01-15 10:22:29

品牌	Logo	应用领域
XICOR		监控可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
23页	106K
描述
Dual Voltage CPU Supervisor with 64K Password Protected EEPROM

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数据手册

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X46402V8E-2.9 数据手册

Preliminary Information

64K

X46402

Dual Voltage CPU Supervisor with 64K Password Protected EEPROM

FEATURES

DESCRIPTION

• Dual Voltage Detection and Reset Assertion

—Low Vcc Monitor

—Low V2MON Monitor

—Low Vcc Block of EEPROM Writes

—RESET Signal Valid down to Vcc=1V

• Selectable Watchdog Timer

—150ms, 450ms, 1s, 5s, 10s, 20s, 1min, OFF

• Volatile Flag shows Watchdog/Low Voltage Reset

• 64kbit 2-wire Serial EEPROM

The X46402 combines several functions into one device.

The ﬁrst is a dual voltage CPU supervisor plus 64Kbit

serial EEPROM memory with password protected write

and read operations. The size of the password protected

area is selectable by 3 control bits. A Write Protect (WP)

pin in conjunction with a WPEN bit provides hardware

OTP control of the conﬁguration of the array. Password

protected areas require 64 bit read or write passwords

prior to access. The eighth illegal password entry

(regardless of the number of correct entries) sets an OTP

tamper bit.This bit is one of the 32 bits in the Device ID.

—1MHz Serial Interface speed

—64-Byte Page Write Mode

• Two 64-Byte OTP memory blocks

—Requires 64-bit OTP password to write

• Adjustable size Password Protected Array

—64 Bit Read and Write Array Passwords

—Non-password protected array area

• 8 count tamper counter for invalid passwords

• Operates at 2.5-3.7V

A secondary voltage monitor circuit activates a V2FAIL

pin when the secondary supply voltage drops below a

V2trip voltage. This circuit is primarily intended to detect

the immediate loss of the battery supply.

A low Vcc voltage detect circuit activates a RESET pin

when Vcc drops below a V

voltage. This signal also

TRIP

• 8L TSSOP package

blocks read or write operations.

A watchdog timer with the time period controlled by three

bits provides several possible time out periods from

150ms to 1 minute.

Functional Diagram

WATCHDOG

Write Control

TIMER RESET

Password Logic

HV Generation

Timing and Control

RESET &

WATCHDOG

RESET

TIMEBASE

Write Password Area

(Bytes)

Command

Decode

and

Control

Logic

(64, 128, 256, 512,

POWER ON AND

LOW VOLTAGE

RESET

2K, 4K, All, None)

SCL

SDA

No Password Area

GENERATION

Control

OTP array 1

OTP array 2

Passwords

V2FAIL

V2MON

Y Decoder

V_2TRIP

Data Register

Vcc

(Vcc) Control Signal

V_TRIP

Xicor, Inc. 1994, 1995, 1996, 1998 Patents Pending

9900-3003 5 1/11/00 CM

Characteristics subject to change without notice

12 3 4 5 6 7...23

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