X46402V8E-2.9

更新时间： 2024-02-09 10:34:49

品牌	Logo	应用领域
XICOR		监控可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
23页	106K
描述
Dual Voltage CPU Supervisor with 64K Password Protected EEPROM

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中文翻译

获取价格

数据手册

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X46402V8E-2.9 数据手册

X46402

Preliminary Information

The Control Register contains bits that control the watch-

dog timer and the hardware write protect features and is

formatted as follows:

µC

Vcc

Volt

Reg

OTP Mode

Enabled

Pin1

WPEN FLB WD2 WD1 WD0 BL2 BL1 BL0

Vcc

V2MON

SCL

Vss

SCL

Write Protect Enable bit (WPEN)

SDA

V2FAIL

RESET

The WP pin, in conjuction with a WPEN bit programmed

HIGH, provides Hardware Write Protection.This prevents

changes to the control register contents even with a valid

password. When either the WP pin or WPEN bit is LOW,

a 64 bit Array write array password is required to change

the contents of the control register. When both the WP

pin and the WPEN bit are HIGH, the Control Register

cannot be written.

SDA

INTR

RESET

Recommended Connection

ARCHITECTURE

Data Memory

Flag Bit

This 64kbit memory array can be partitioned into pass-

word protected or non-password protected areas. When

password protected, the contents are readable after

sending a “Memory Read” password. The contents of a

password protected portion of the memory array are

writeable with a “Memory Write” Password. This array is

re-writable up to the limit of the EEPROM endurance.

The ﬂag bit is a volatile bit. It can be used to determine if

a reset condition was due to a power failure or watchdog

reset condition. If power fails (i.e. the internal low voltage

detect signal goes active), the bit is set to ’0’. This bit is

also set or reset by a Control Register write operation. A

watchdog reset does not change the state of the ﬂag bit.

OTP

Watchdog Timer Control

The second section of memory consists of two 64-byte

arrays, each writable only once. These arrays are always

password protected. Reading from either of these arrays

requires the use of an “OTP Read” password. Both

arrays can be read with a single operation. Writing either

array requires an “OTP Write” Password. Writing more

than 64 bytes to each array results in the data “wrapping”

around and over-writing previous values.

The Watchdog time-out period is controlled by the bits

WD2, WD1, and WD0. See the following Table.

Table 1. Watchdog Time Control Bits

Control Register Bits

Watchdog Time-out

(Typical)

WD2

WD1

WD0

1 Second

450 Milliseconds

150 Milliseconds

Disabled

Array

Address

OTP Array 1

OTP Array 2

0000h - 003Fh

0040h - 007Fh

1 minute

20 seconds

10 seconds

5 seconds

Control Register

A password protected read or write array command at

address FFFFh reads or writes the Control Register.

Since the control register contains information relating to

the password protection, it is necessary to use the Array

passwords to access the control register.

1 234 5 6 7...23

中文翻译

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与X46402V8E-2.9相关器件

型号	品牌	获取价格	描述	数据表
X46402V8E-3.1	XICOR	获取价格	Dual Voltage CPU Supervisor with 64K Password Protected EEPROM
X46402V8E-3.1A	XICOR	获取价格	Dual Voltage CPU Supervisor with 64K Password Protected EEPROM
X4643	XICOR	获取价格	CPU Supervisor with 64K EEPROM
X4643	INTERSIL	获取价格	CPU Supervidor with 64K EEPROM
X4643S8	INTERSIL	获取价格	CPU Supervidor with 64K EEPROM
X4643S8-2.7	INTERSIL	获取价格	CPU Supervidor with 64K EEPROM
X4643S8-2.7A	INTERSIL	获取价格	CPU Supervidor with 64K EEPROM
X4643S8-2.7AT1	RENESAS	获取价格	1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8, PLASTIC, SOIC-8
X4643S8-4.5A	INTERSIL	获取价格	CPU Supervidor with 64K EEPROM
X4643S8I	INTERSIL	获取价格	CPU Supervidor with 64K EEPROM

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