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X4163S8-4.5A PDF预览

X4163S8-4.5A

更新时间： 2024-02-09 17:03:57
品牌 Logo 应用领域
英特矽尔 - INTERSIL 光电二极管监控可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
21页 330K
描述
CPU Supervisor with 16K EEPROM

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X4163S8-4.5A 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：PLASTIC, SOIC-8Reach Compliance Code：unknown
风险等级：5.76可调阈值：YES
模拟集成电路 - 其他类型：POWER SUPPLY MANAGEMENT CIRCUITJESD-30 代码：R-PDSO-G8
JESD-609代码：e0长度：4.89 mm
信道数量：1功能数量：1
端子数量：8最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE认证状态：Not Qualified
座面最大高度：1.75 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL宽度：3.9 mm
Base Number Matches：1

X4163S8-4.5A 数据手册

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X4163, X4165  
Figure 4. V  
Programming Sequence  
TRIP  
VTRIP Programming  
Execute  
Reset VTRIP  
Sequence  
Set VCC = VCC Applied =  
Desired VTRIP  
New VCC Applied =  
Old VCC Applied + Error  
New VCC Applied =  
Old VCC Applied - Error  
Execute  
Set VTRIP  
Sequence  
Execute  
Reset VTRIP  
Sequence  
Apply 5V to VCC  
Decrement VCC  
(VCC = VCC - 50mV)  
NO  
RESET pin  
goes active?  
YES  
Error ≤ –Emax  
Error ≥ Emax  
Measured VTRIP  
Desired VTRIP  
-
–Emax < Error < Emax  
DONE  
Emax = Maximum Allowed VTRIP Error  
Control Register  
The user must issue a stop after sending this byte to  
the register to initiate the nonvolatile cycle that stores  
WD1, and WD0. The X4163/5 will not acknowledge  
any data bytes written after the first byte is entered.  
The Control Register provides the user a mechanism  
for changing the Block Lock and Watchdog Timer set-  
tings. The Block Lock and Watchdog Timer bits are  
nonvolatile and do not change when power is  
removed.  
The state of the Control Register can be read at any  
time by performing a random read at address FFFFh.  
Only one byte is read by each register read operation.  
The X4163/5 resets itself after the first byte is read.  
The master should supply a stop condition to be con-  
sistent with the bus protocol, but a stop is not required  
to end this operation.  
The Control Register is accessed at address FFFFh. It  
can only be modified by performing a byte write opera-  
tion directly to the address of the register and only one  
data byte is allowed for each register write operation.  
Prior to writing to the Control Register, the WEL and  
RWEL bits must be set using a two step process, with  
the whole sequence requiring 3 steps. See "Writing to  
the Control Register" below.  
7
6
5
4
3
2
1
0
WPEN WD1 WD0 BP1 BP0 RWEL WEL BP2  
FN8120.0  
5
April 13, 2005  
12345678...21

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