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X4163S8-4.5A

更新时间： 2024-02-23 06:13:49
品牌 Logo 应用领域
英特矽尔 - INTERSIL 光电二极管监控可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
21页 330K
描述
CPU Supervisor with 16K EEPROM

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X4163S8-4.5A 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：PLASTIC, SOIC-8Reach Compliance Code：unknown
风险等级：5.76可调阈值：YES
模拟集成电路 - 其他类型：POWER SUPPLY MANAGEMENT CIRCUITJESD-30 代码：R-PDSO-G8
JESD-609代码：e0长度：4.89 mm
信道数量：1功能数量：1
端子数量：8最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE认证状态：Not Qualified
座面最大高度：1.75 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL宽度：3.9 mm
Base Number Matches：1

X4163S8-4.5A 数据手册

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X4163, X4165  
PRINCIPLES OF OPERATION  
Power On Reset  
WATCHDOG TIMER  
The Watchdog Timer circuit monitors the microproces-  
sor activity by monitoring the SDA and SCL pins. The  
microprocessor must toggle the SDA pin HIGH to  
LOW periodically, while SCL is HIGH (this is a start bit)  
prior to the expiration of the watchdog time out period to  
prevent a RESET/RESET signal. The state of two non-  
volatile control bits in the Status Register determine  
the watchdog timer period. The microprocessor can  
change these watchdog bits, or they may be “locked”  
by tying the WP pin HIGH.  
Application of power to the X4163/5 activates a Power  
On Reset Circuit that pulls the RESET/RESET pin  
active. This signal provides several benefits.  
– It prevents the system microprocessor from starting  
to operate with insufficient voltage.  
– It prevents the processor from operating prior to sta-  
bilization of the oscillator.  
– It allows time for an FPGA to download its configura-  
tion prior to initialization of the circuit.  
EEPROM INADVERTENT WRITE PROTECTION  
– It prevents communication to the EEPROM, greatly  
reducing the likelihood of data corruption on power up.  
When RESET/RESET goes active as a result of a low  
voltage condition or Watchdog Timer Time Out, any in-  
progress communications are terminated. While  
RESET/RESET is active, no new communications are  
allowed and no nonvolatile write operation can start.  
Nonvolatile writes in-progress when RESET/RESET  
goes active are allowed to finish.  
When V  
exceeds the device V  
threshold value  
CC  
TRIP  
for  
200ms  
(nominal)  
the  
circuit  
releases  
RESET/RESET allowing the system to begin operation.  
LOW VOLTAGE MONITORING  
Additional protection mechanisms are provided with  
memory Block Lock and the Write Protect (WP) pin.  
These are discussed elsewhere in this document.  
During operation, the X4163/5 monitors the V level  
and asserts RESET/RESET if supply voltage falls  
CC  
below a preset minimum V  
. The RESET/RESET  
TRIP  
signal prevents the microprocessor from operating in a  
power fail or brownout condition. The RESET/RESET  
signal remains active until the voltage drops below 1V.  
V
THRESHOLD RESET PROCEDURE  
CC  
The X4163/5 is shipped with a standard V threshold  
(V  
operating and storage conditions. However, in applica-  
tions where the standard V is not exactly right, or if  
CC  
It also remains active until V  
returns and exceeds  
CC  
) voltage. This value will not change over normal  
TRIP  
V
for 200ms.  
TRIP  
TRIP  
higher precision is needed in the V  
value, the  
TRIP  
X4163/5 threshold may be adjusted. The procedure is  
described below, and uses the application of a nonvol-  
atile control signal.  
Figure 1. Set V  
Level Sequence (V = desired V values WEL bit set)  
TRIP  
TRIP  
CC  
VP = 12-15V  
WP  
0 1 2 3 4 5 6 7  
0 1 2 3 4 5 6 7  
0 1 2 3 4 5 6 7  
0 1 2 3 4 5 6 7  
SCL  
SDA  
A0h  
00h  
01h  
00h  
FN8120.0  
3
April 13, 2005  
1234567...21

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