Datasheet > X4163S8-2.7A-T1

X4163S8-2.7A-T1

更新时间： 2024-01-10 16:21:50

品牌	Logo	应用领域
瑞萨 - RENESAS		光电二极管
页数	文件大小	规格书
22页	342K
描述
1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8, SOIC-8

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X4163S8-2.7A-T1 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	SOP,	针数：	8
Reach Compliance Code：	not_compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.76
Is Samacsys：	N	其他特性：	RESET THRESHOLD VOLTAGE IS 2.92V
可调阈值：	NO	模拟集成电路 - 其他类型：	POWER SUPPLY MANAGEMENT CIRCUIT
JESD-30 代码：	R-PDSO-G8	JESD-609代码：	e0
长度：	4.9022 mm	湿度敏感等级：	1
信道数量：	1	功能数量：	1
端子数量：	8	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	峰值回流温度（摄氏度）：	240
认证状态：	Not Qualified	座面最大高度：	1.7272 mm
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	2.7 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	宽度：	3.9116 mm
Base Number Matches：	1

X4163S8-2.7A-T1 数据手册

X4163, X4165

read. The master should supply a stop condition to be

consistent with the bus protocol, but a stop is not

required to end this operation.

zeroes to the other bits of the control register. Once

set, WEL remains set until either it is reset to 0 (by

writing a “0” to the WEL bit and zeroes to the other bits

of the control register) or until the part powers up

again. Writes to the WEL bit do not cause a nonvolatile

write cycle, so the device is ready for the next opera-

tion immediately after the stop condition.

WPEN WD1 WD0 BP1 BP0 RWEL WEL BP2

BP2, BP1, BP0: Block Protect Bits (Nonvolatile)

WD1, WD0: Watchdog Timer Bits

The Block Protect Bits, BP2, BP1 and BP0, determine

which blocks of the array are write protected. A write to

a protected block of memory is ignored. The block pro-

tect bits will prevent write operations to the following

segments of the array.

The bits WD1 and WD0 control the period of the

Watchdog Timer. The options are shown below.

WD1

WD0

Watchdog Time Out Period

1.4 seconds

Protected Addresses

600 milliseconds

(Size)

Array Lock

None

200 milliseconds

None (factory setting)

None

disabled (factory setting)

None

Write Protect Enable

0000h - 7FFh (2K bytes)

000h - 03Fh (64 bytes)

000h - 07Fh (128 bytes)

000h - 0FFh (256 bytes)

000h - 1FFh (512 bytes)

Full Array (All)

First Page (P1)

First 2 pgs (P2)

First 4 pgs (P4)

First 8 pgs (P8)

These devices have an advanced Block Lock scheme

that protects one of five blocks of the array when

enabled. It provides hardware write protection through

the use of a WP pin and a nonvolatile Write Protect

Enable (WPEN) bit.

The Write Protect (WP) pin and the Write Protect

Enable (WPEN) bit in the Control Register control the

programmable Hardware Write Protect feature. Hard-

ware Write Protection is enabled when the WP pin and

the WPEN bit are HIGH and disabled when either the

WP pin or the WPEN bit is LOW. When the chip is

Hardware Write Protected, nonvolatile writes to the

block protected sections in the memory array cannot be

written and the block protect bits cannot be changed.

Only the sections of the memory array that are not

block protected can be written. Note that since the

WPEN bit is write protected, it cannot be changed

back to a LOW state; so write protection is enabled as

long as the WP pin is held HIGH.

RWEL: Register Write Enable Latch (Volatile)

The RWEL bit must be set to “1” prior to a write to the

Control Register.

WEL: Write Enable Latch (Volatile)

The WEL bit controls the access to the memory and to

the Register during a write operation. This bit is a vola-

tile latch that powers up in the LOW (disabled) state.

While the WEL bit is LOW, writes to any address,

including any control registers will be ignored (no

acknowledge will be issued after the Data Byte). The

WEL bit is set by writing a “1” to the WEL bit and

Table 1. Write Protect Enable Bit and WP Pin Function

Memory Array not

Block Protected

Memory Array Block

WPEN

Protected

WPEN Bit

Writes OK

Protection

Software

LOW

HIGH

Writes OK

Writes Blocked

Writes OK

Software

Writes Blocked

Hardware

FN8120.2

November 26, 2007

1...5 6 789 10 11...22

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与X4163S8-2.7A-T1相关器件

型号	品牌	描述	获取价格	数据表
X4163S8-4.5A	INTERSIL	CPU Supervisor with 16K EEPROM	获取价格
X4163S8-4.5A	RENESAS	1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8, SOIC-8	获取价格
X4163S8I	INTERSIL	CPU Supervisor with 16K EEPROM	获取价格
X4163S8I	RENESAS	1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8, SOIC-8	获取价格
X4163S8I-2.7	INTERSIL	CPU Supervisor with 16K EEPROM	获取价格
X4163S8I-2.7A	INTERSIL	CPU Supervisor with 16K EEPROM	获取价格

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