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X28C512JI-12T2 PDF预览

X28C512JI-12T2

更新时间: 2024-10-03 14:21:07
品牌 Logo 应用领域
瑞萨 - RENESAS 可编程只读存储器电动程控只读存储器电可擦编程只读存储器内存集成电路
页数 文件大小 规格书
24页 158K
描述
EEPROM, 64KX8, 120ns, Parallel, CMOS, PQCC32, PLASTIC, LCC-32

X28C512JI-12T2 数据手册

 浏览型号X28C512JI-12T2的Datasheet PDF文件第2页浏览型号X28C512JI-12T2的Datasheet PDF文件第3页浏览型号X28C512JI-12T2的Datasheet PDF文件第4页浏览型号X28C512JI-12T2的Datasheet PDF文件第5页浏览型号X28C512JI-12T2的Datasheet PDF文件第6页浏览型号X28C512JI-12T2的Datasheet PDF文件第7页 
512K  
64K x 8 Bit  
X28C512/X28C513  
5 Volt, Byte Alterable EEPROM  
FEATURES  
• Two PLCC and LCC pinouts  
—X28C512  
• X28C010 EPROM pin compatible  
—X28C513  
• Access time: 90ns  
• Simple byte and page write  
—Single 5V supply  
• No external high voltages or V control  
circuits  
—Self-timed  
• Compatible with lower density EEPROMs  
PP  
DESCRIPTION  
• No erase before write  
• No complex programming algorithms  
• No overerase problem  
• Low power CMOS  
—Active: 50mA  
—Standby: 500µA  
• Software data protection  
—Protects data against system level inadvertent  
writes  
• High speed page write capability  
• Highly reliable Direct Writecell  
—Endurance: 100,000 write cycles  
—Data retention: 100 years  
• Early end of write detection  
DATA polling  
The X28C512/513 is a 64K x 8 EEPROM, fabricated  
with Xicor’s proprietary, high performance, floating  
gate CMOS technology. Like all Xicor programmable  
nonvolatile memories, the X28C512/513 is a 5V only  
device. The X28C512/513 features the JEDEC  
approved pin out for byte wide memories, compatible  
with industry standard EPROMS.  
The X28C512/513 supports a 128-byte page write  
operation, effectively providing a 39µs/byte write cycle  
and enabling the entire memory to be written in less  
than 2.5 seconds. The X28C512/513 also features  
DATA Polling and Toggle Bit Polling, system software  
support schemes used to indicate the early completion  
of a write cycle. In addition, the X28C512/513 supports  
the software data protection option.  
Toggle bit polling  
BLOCK DIAGRAM  
512Kbit  
EEPROM  
Array  
X Buffers  
Latches and  
Decoder  
A –A  
7
15  
I/O Buffers  
and Latches  
Y Buffers  
Latches and  
Decoder  
A –A  
0
6
I/O –I/O  
0
7
Data Inputs/Outputs  
CE  
Control  
Logic and  
Timing  
OE  
WE  
V
V
CC  
SS  
Characteristics subject to change without notice. 1 of 24  
REV 1.0 6/27/00  
www.xicor.com  

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